Instruction manual

9.6.5.1 Unaligned DMA Write Operation
Two registers are provided for unaligned data during DMA writes:
• DMA unaligned data[0] (Section 8.2.5)
DMA unaligned data[0] contains the unaligned data at the beginning the
transfer. The least significant byte has a mask for writing this data to
memory. The address is the DMA address that was originally written to the
ASIC. This address must be made available to software.
• DMA unaligned data[1] (Section 8.2.5)
DMA unaligned data[1] contains the unaligned data at the end of the transfer.
The most significant byte has a mask for writing this data to memory. The
address is the address currently in the DMA address register. False data
may appear in this register, if the transfer count was odd and the 53C94 was
configured to send the last byte.
9.6.5.2 Interrupt Service
If interrupt prefetching is enabled (see above), the ASIC will prefetch the three
53C94 (or 53CF94-2) registers, status, fifo flags, and interrupt. It will delay
posting an interrupt until this is done. Prefetching will change the state in the
53C94 (or 53CF94-2). Another interrupt will not be processed until the prefetched
interrupt bit in the control interrupt register is cleared.
9.6.6 Aborting Transactions
Before a transaction can be aborted by the resetting of the 53C94 or 53CF94-2,
DMA enable in the control interrupt register must be cleared. Clearing this
bit allows the current burst to complete but prevents additional bursts from
beginning. The ~Reset bit in the CIR can now be asserted to assert reset to the
53C94 (or 53CF94-2) and reset the DMA engine in the ASIC. Software must keep
~Reset asserted for 500 ns.
I/O Programming 9–19