Instruction manual

Table 33 Baud Rate Programming
Baud Divider Value
19.2 K 16
10
10
9600 16
10
22
7200 16
10
30
4800 16
10
46
3600 16
10
62
2400 16
10
94
2000 16
10
113
1800 16
10
126
1200 16
10
190
600 16
10
382
300 16
10
766
150 16
10
1534
134 16
10
1717
110 16
10
2093
75 16
10
3070
50 16
10
4606
The SCC registers are aligned to longwords with data being read and written
from byte 1. For example writing a 0x01234567 to an SCC register sets it to a
value of 45. Reading a register with a value of 45 will return xxxx45xx, where x
= UNPREDICTABLE data.
DMA data is likewise aligned to byte 1. Receive bytes are valid only at the byte 1
position, because bytes are transmitted only from the byte 1 position.
9.5.2.5 DMA for Communication Transmit Port and Printer Port
Two transmit DMA channels are supplied by the IOCTL ASIC:
• A channel for the communication port (all models)
• A channel for the printer port (400/500/600/700/800/900 models only)
Each has its own pointer for accessing buffers in main memory. Communication
DMA occurs a byte at a time on longword boundaries and uses only byte 1 of the
longwords.
Software copies data to a buffer in main memory, sets the pointers to index the
buffer, and enables DMA. The pointer must equal the page-end-address minus
four times the number of bytes to be transmitted:
pointer = page-end-address - (4 * number-bytes-to-transmit)
DMA begins with the pointer address and transmits until the last byte in a 4-KB
page is sent. DMA is disabled and an interrupt set indicating that the DMA has
completed.
I/O Programming 9–11