Instruction manual

The LANCE registers are 16 bits wide and longword-aligned. For example,
a write operation to a register of 12345678 will write 5678 into that register.
Likewise, if a register contains 5678 then a read operation of that register returns
xxxx5678, where x = UNPREDICTABLE data.
LANCE programmed I/O cannot be performed if incorrect information about the
LANCE I/O slot register is provided to the IOCTL subsystem.
Further information about LANCE registers can be found:
Section 7.3.1 describes the LANCE DMA pointer register.
Section 7.5 lists LANCE register addresses.
Section 7.3.17 describes the LANCE I/O slot register.
9.5.2.3 LANCE DMA
LANCE DMA is performed in four-longword bursts, except at the end of a
transaction (one to four longwords) or at the time the descriptor ring is being
accessed, in which case only the low 16 bits are valid.
The addresses in the descriptor ring must always be octaword-aligned, because
the LANCE tries to burst eight 16-bit quantities and crossing page boundaries is
not allowed during a DMA burst. Because of the way the Ethernet DMA pointer
is constructed, the buffers are not contiguous in memory. The next burst transfer
occurs 4 longwords from the end of the previous transfer. This leaves gaps of 4
longwords every 4 longwords.
For a LANCE DMA transmission, 4 longwords are read from memory and the
IOCTL then passes consecutive 16-bit chunks to the LANCE until the request is
de-asserted or the 4 longwords have been fed to the LANCE.
For a LANCE DMA reception, the I/O controller groups pairs of 16 bits into one
32-bit chunk and stores the chunks in the data registers, beginning with D0. The
data is buffered until the DMA request is deasserted or the eight 16-bit quantities
have been received. The data is then written into memory by DMA.
Fewer than four longwords can be transmitted. The number of longwords in the
transfer equals the number of 16-bit chunks divided by two. If an odd number
of chunks is transmitted, then the upper sixteen bits of the last longword are
invalid. For example, if the LANCE supplied only five 16-bit quantities, then
only three longwords are written and the upper 16 bits of the last longword are
invalid.
The upper and lower bits of the DMA address pointer (see Section 7.3.1) originate
in different sources. The LANCE generates the lower 16 bits; the upper 13 bits
are located in the IOCTL ASIC. Software should initialize the upper bits of the
LANCE pointer register only once, placing the network buffer in memory at some
fixed address.
If an error occurs, DMA is terminated and error information is loaded into the
system interrupt register, as in Section 7.3.12.
9.5.2.4 Serial Communications Controller (SCC)
Two Zilog SCC (Z85C30) dual UARTS support the keyboard, mouse and printer in
workstation configurations; they also support a communication port for optional
serial peripherals. The serial transmitters are doubled-buffered; each receiver
has a 3-byte FIFO buffer. The baud rate of each serial line is programmable
(50-19.2K baud) by the setting of bits in the time-constant register. The following
table lists programming values for common baud rates. They are computed from
the Pclk frequency of 7.3728 MHz.
9–10 I/O Programming