Instruction manual

Bits <31:16> reflect various DMA conditions; bits <15:0> reflect the status of
specific system devices and may be individually masked. See Section 7.3.12
for further information.
• SSR
Bits <31:16> enable DMAs and determine the direction of some types of DMA
transfers. See Section 7.3.11 for further information.
9.5.2 I/O Programming and System FEPROM
JUNKIO FEPROMs differ according to model.
• 300 models contain 768 KB of Flash ROMs, configured as 3 different 256-KB
Flash ROMs. ROMs are selected by setting or clearing bit <27> of the SSR.
A 256-KB FEPROM contains the powerup test, system initialization, and
console software.
• 400/500/600/700/800/900 models have a 256-KB FEPROM containing the
powerup test, system initialization, and console software.
Since the FEPROMs do not contain parity, ROM software should contain a
checksum that is verified during system restart. The IOCTL can perform
single-byte reads and writes or quad-byte reads with the system ROM.
An access to the ROM slot with SSR<26> set to 0 causes four read operations
to be performed on an 8-bit wide ROM. The IOCTL places the four bytes in one
32-bit word, with the first byte in the least significant byte position. A longword
is returned to the CPU, and software reads the ROM one longword at a time.
An access to the ROM slot with SSR<26> set to 1 enables single ROM access. A
read or write operation from or to ROM space results in a single access to the
ROM, with the ‘‘byte’’ signals being driven with the contents of SSR<25:24>.
Note
Write operations to ROM space are always single-access, regardless of the
contents of SSR<26>. This mode is used to modify the Flash ROMs. The
access is otherwise identical to generic device access.
Disabling the hardware jumper W1 disables write operations to the ROM.
9.5.2.1 Ethernet Station Address ROM
The Ethernet Station Address ROM (ESAR) is located at 1.A008.0000 in 300
models and at 1.E008.0000 in 400/500/600/700/800/900 models . The ROM
consists of 32 8-bit locations and is longword-aligned. The data is presented
on byte 0, bits 0 through 7 of the data bus. The ESAR ROM is in a socket.
Section 7.4 describes the ROM.
9.5.2.2 LANCE Interface
The LANCE manages the transmission and reception of packets by means of
a dedicated buffer in main memory. The CPU usually communicates with the
LANCE through this shared buffer.
The LANCE supports 4-longword read and write operations in DMA mode and
word (16-bits) read and write operations in the programmed I/O mode. DMA must
be programmed to start on 4-longword aligned boundaries; otherwise buffers may
be overwritten and/or misaligned.
I/O Programming 9–9