Instruction manual

Bit Access Reset Description
12 R/W 0 In 300 models, Reserved. 300 models do not support
TURBOchannel parity.
In 400/500/600/700/800/900 models, SCSI[0] DMA
buffer parity test mode; when set, bad parity is
written into the SCSI[0] DMA buffer during DMA
receives from the 53C94. During DMA reads, parity
always comes from the TURBOchannel. This allows
bad parity to be asserted on the TURBOchannel
during DMA write data cycles.
13 R/W 0 SCSI[1] In 300 models, Reserved. 300 models do not
support TURBOchannel parity.
In 400/500/600/700/800/900 models, DMA buffer
parity test mode; when set, bad parity is written
into the SCSI[1] DMA buffer during DMA receives
from the 53C94. During DMA reads, parity always
comes from the TURBOchannel. This allows bad
parity to be asserted on the TURBOchannel during
DMA write data cycles.
14 R/W 0 DB parity test mode
When set, bad parity is asserted on the bus to the
53C94s.
15 R/W 0 In 300 models, reserved. 300 models do not support
TURBOchannel parity.
In 400/500/600/700/800/900 models, TURBOchannel
parity test mode; when set, bad parity is asserted on
the TURBOchannel during I/O read data and DMA
address cycles.
16 R/W0C 0 SCSI[0] 53C94 DREQ
Set when the SCSI[0] 53C94 has asserted its DREQ
signal.
17 R/W0C 0 SCSI[1] 53C94 DREQ
Set when the SCSI[1] 53C94 has asserted its DREQ
signal.
18 R/W0C 0 SCSI[0] 53C94/53CF94-2 interrupt
Set when the SCSI[0] 53C94 has asserted its
interrupt signal and any pending DMA transactions
have been completed.
19 R/W0C 0 SCSI[1] 53C94/53CF94-2 interrupt
Set when the SCSI[1] 53C94/53CF94-2 has asserted
its interrupt signal and pending DMA transactions
have completed.
20 R/W0C 0 Reserved. The enable setting for this bit must be
zero.
21 R/W0C 0 Reserved. The enable setting for this bit must be
zero.
22 R/W0C 0 SCSI[0] DMA error
Set when a DMA error occurs for SCSI[0].
23 R/W0C 0 SCSI[1] DMA error
Set when a DMA error occurs for SCSI[1].
TURBOchannel Dual SCSI ASIC 8–5