Instruction manual

8.2.1 Control Interrupt Register (CIR)—1.8004.0000/1.C004.0000
The control interrupt register (CIR) consists of two sections:
• The most significant 16 bits are the interrupt section. These bits are set by
hardware and can be cleared only by the system writing 0; writing 1 has no
effect.
• The less significant 16 bits are the control section. Parity test mode forces bad
parity instead of the normal odd-generated parity. SCSI resets terminate the
current DMA transaction. The DMA enable must be cleared before reset is
asserted. Clearing the DMA enable allows a current DMA burst to complete
in an orderly manner before the reset is performed. Reset is asserted when
the bit is clear. SCSI DMA enables allow DMA transactions. If disabled, the
DMA buffers are not filled with data and no TURBOchannel DMA bursts are
initiated. Interrupts from the 53C94/53CF94-2 nonetheless function normally.
The register’s format and contents are:
0031
MR−0097−93RAGS
INTERRUPT CONTROL
1516
Bit Access Reset Description
2:0 R/W 0 General purpose output<2:0>. Reserved.
3 R/W 0 Serial transmit disable
When clear, the EIA driver on the serial lines is
active.
7:4 R 0 General purpose input<3:0>. Read as 1111.
8 R/W 0 SCSI[0] DMA enable, disable(0)/enable(1)
When set, DMA transactions for SCSI[0] can take
place. Cleared if any SCSI[0] DMA error interrupt
is attempting to interrupt the TURBOchannel.
9 R/W 0 SCSI[1] DMA enable(1), disable(0)
When set, DMA transactions for SCSI[1] can take
place. Cleared if any SCSI[1] DMA error interrupt
is attempting to interrupt the TURBOchannel.
10 R/W 0 Enable/disable reset (SCSI[0] )
When clear, active DMA transactions for SCSI[0]
are aborted.
11 R/W 0 SCSI[1] Enable/disable reset (SCSI[1]).
When clear, active DMA transactions for SCSI[1]
are aborted.
8–4 TURBOchannel Dual SCSI ASIC