Instruction manual

7.3.15 ISDN Data Transmit Register—1.A004.0140/1.E004.0140
This register contains the data that are transferred from memory during DMA.
The data is loaded into the transmit shift register (see Section 9.5.2.8 for more
detail.)
The register’s format and contents are:
Bits Access Reset Function
23:0 R/W UNP ISDN transmit data
31:24 0 Reserved, returns 0 when read
7.3.16 ISDN Data Receive Register—1.A004.0150/1.E004.0150
This register contains the data that was located in the receive shift register when
sfs was asserted (see Section 9.5.2.8).
The register’s format and contents are:
Bits Access Reset Function
23:0 R/W UNP ISDN receive data
31:24 0 Reserved, returns 0 when read
7.3.17 LANCE I/O Slot Register—1.A004.0160/1.E004.0160
This register contains the address of the LANCE I/O slot. This and other DMA
slot registers were included in the hardware for future implementations of the
address decoding.
The register’s format and contents are:
Bits Access Reset Function
3:0 R/W UNP Chip selects. Control hardware decoding of chip
selects for LANCE I/O. Must be set to 3; otherwise,
LANCE registers cannot be written to.
9:4 R/W UNP Hardware address supplied for LANCE I/O read
operations. Must be set to 0.
31:10 0 Reserved; returns 0 when read
7–16 IOCTL ASIC and System Registers