Instruction manual

Bits Access Function
31 R/W0C Communication port 1 (SCC0) transmit page end interrupt
When set, disables DMA. When clear, enables DMA. When enabled,
the DMA transmitter transmits bytes until the pointer reaches a 4-KB
page boundary. It then stops DMA and interrupts the processor. To
restart, this bit must be cleared by writing 0; writing 1 has no effect.
7.3.13 System Interrupt Mask Register—1.A004.0120/1.E004.0120
The register’s format and contents are:
Bits Access Reset Function
31:0 R/W 0 Interrupt Mask
Bits Function
<31:0> If 0, these bits mask the corresponding interrupt observable in the SIR. Bit
<0> masks SIR<0>, bit <1> masks SIR<1>, and so on. The Mask does not
prevent an interrupt from being flagged in the SIR; rather, it keeps the CPU
from being interrupted. The interrupt mask is set to 0 on powerup, masking
all interrupts. Software must enable interrupts by setting the corresponding
bit to 1.
7.3.14 System Address Register—1.A004.0130/1.E004.0130
The system address register contains a version of the address from the current
I/O read or write transaction. It is readable for test purposes only. Write
operations to this register are not allowed.
The register’s format and contents in 300 models are:
Table 18 System Address Register (300 Models)
Bits Access Function
4:0 Reserved, returns 0 when read
24:5 R/W TURBOchannel address
31:25 Reserved, returns 0 when read
The register’s format and contents in the 400/500/600/700/800/900 models are:
Bits Access Reset Function
4:0 0 Reserved, returns 0 when read
31:5 R TURBOchannel address
IOCTL ASIC and System Registers 7–15