Instruction manual

Bits Access Function
24 R/W0C In 300 models, reserved.
In 400/500/600/700/800/900 models, printer port receive DMA overrun
This bit is set and the DMA disabled, as soon as the receive DMA
pointer associated with printer port reaches a page boundary. To
restart, this bit must be cleared by writing a 0; writing a 1 has no
effect. Note that bit <25> is set whenever this bit is set.
25 R/W0C In 300 models, reserved
In 400/500/600/700/800/900 models, printer port receive half page
interrupt
This bit is set as soon as the receive DMA pointer associated with
printer port reaches a half-page boundary (2 KB). Software must then
disable DMA, load a new pointer, and restart DMA. This bit may
be cleared by writing a 0; Writing a 1 has no effect. Note that this
bit will always be set when bit 24 is set. The setting of this bit is
informational only and does not stop the DMA.
26 R/W0C In 300 models, reserved
In 400/500/600/700/800/900 models, printer port transmit DMA
memory read error
This bit is set and the DMA disabled, if a parity, page-crossing, or
maximum transfer length error occurs during a Communication
transmit port 2 DMA operation. The DMA pointer contains the
error address. Check the appropriate memory sections for more
information. To restart, software must clear this bit by writing a 0;
writing a 1 has no effect.
27 R/W0C In 300 models, reserved.
In 400/500/600/700/800/900 models, printer port transmit page end
interrupt
The printer port transmit DMA logic generates this interrupt. When
enabled, the DMA transmitter transmits bytes until the pointer
reaches a page boundary. It then stops DMA and interrupts the
processor. Setting this bit disables DMA. This bit may be cleared by
writing a 0; writing a 1 has no effect. Clearing this bit restarts the
DMA, if the DMA enable is bit is still on.
28 R/W0C Communication port 1 (SCC0) receive DMA page overrun
This bit is set and DMA disabled, as soon as the receive DMA pointer
associated with communication port 1 reaches a page boundary. To
restart DMA, this bit must be cleared by writing a 0; writing a 1 has
no effect. Note that bit <29> is set, whenever this bit is set.
29 R/W0C Communication port 1 (SCC0) receive half page interrupt
This bit is set, as soon as the receive DMA pointer associated with
communication port 1 reaches a half page (2 KB) boundary. Software
must disable DMA, load a new pointer, and restart DMA without
being interrupted. This bit may be cleared by writing a 0; writing a
1 has no effect. The setting of this bit is informational only and does
not stop the DMA.
30 R/W0C Communication port 1 (SCC0) transmit DMA memory read error.
This bit is set and the DMA disabled, if a parity, page-crossing, or
maximum transfer length error occurs during a Communication
transmit port 1 DMA operation. The DMA pointer contains the error
address. Check the memory sections for more information. To restart,
software must clear this bit by writing a 0; writing a 1 has no effect.
7–14 IOCTL ASIC and System Registers