Instruction manual

7.3.1 LANCE DMA Pointer Register (LDP)—1.A004.0020/1.E004.0020
The register’s format and contents are:
Bits Access Reset Function
4:0 R/W UNP DMA physical address <33:29>
19:5 R/W UNP LANCE DMA physical address <16:2>, LANCE
Address <15:1>
31:20 R/W UNP DMA physical address <28:17>
Bits Function
4:0 The upper 5 bits of the pointer that the DMA engine uses to access the
network buffer; can be changed only by writes from the CPU.
19:5 The lower 15 bits of the pointer the DMA engine uses to access the
network buffer (physical address bits <15:2>); this address originated as
<14:1> written by the LANCE before every burst or descriptor access and
then shifted left one position to align the descriptors on word boundaries.
This register may be written to for test reasons; however, subsequent read
operations may not equal the written contents, because LANCE may have
in turn written to the pointer register.
31:20 The middle 12 bits of the pointer used by the DMA engine to access the
network buffer; can be changed only by writes from the CPU.
7.3.2 Communication Port 1 Transmit DMA Pointer—1.A004.0030/1.E004.0030
This pointer points to the word containing the next byte to be transmitted
through communication port 1. The register’s format and contents are:
Bits Access Reset Function
4:0 R/W UNP DMA physical address <33:29>
31:5 R/W UNP DMA physical address <28:2>
7.3.3 Communication Port 1 Receive DMA Pointer—1.A004.0040/1.E004.0040
This pointer points to the word to contain the next byte to be received from
communication port 1. The register’s format and contents are:
Bits Access Reset Function
4:0 R/W UNP DMA physical address <33:29>
31:5 R/W UNP DMA physical address <28:2>
IOCTL ASIC and System Registers 7–7