Instruction manual

46 Dense I/O Space Addressing: 300 Models ...................... A–2
47 Sparse I/O Space Addressing: 400/500/600/700/800/900 Models ...... A–3
48 Sparse I/O Space Addressing: 300 Models ...................... A–3
Tables
1 Conventions Used in this Guide .............................. xv
2 Bit Name Conventions Used in this Guide...................... xvi
3 System Jumpers. . ........................................ 1–5
4 Memory Address Spaces.................................... 2–2
5 Memory Address Space Components . . . ....................... 2–2
6 300 Model I/O Address Map . ................................ 2–4
7 400/500/600/700/800/900 Models I/O Address Map . ............... 2–5
8 I/O Interface Registers (300 Models) . . . ....................... 3–1
9 TURBOchannel Control and Status Registers (300 Models). . ....... 3–2
10 TURBOchannel Control and Status Registers
(400/500/600/700/800/900) Models ............................ 3–8
11 IMR—1.C281.FFFC ....................................... 3–16
12 IR—1.D4C0.0000 . ........................................ 3–18
13 Scatter/Gather Registers . . . ................................ 5–1
14 CXTurbo Address Map ..................................... 6–3
15 Frame Buffer and Video Register Map . . ....................... 6–5
16 IOCTL Address Map ...................................... 7–3
18 System Address Register (300 Models). . ....................... 7–15
19 Ethernet Station Address ROM Addresses (400/500/600/700/800/900
Models) ................................................ 7–18
20 Ethernet Station Address ROM Addresses (300 Models) ........... 7–19
21 LANCE Register Addresses (400/500/600/700/800/900 Models) ...... 7–21
22 LANCE Register Addresses (300 Models)....................... 7–21
23 SCC Register Addresses (300 Models) . . ....................... 7–21
24 SCC Register Addresses (400/500/600/700/800/900 Models) . . ....... 7–21
25 RTC Register Addresses (300 Models) . . ....................... 7–23
26 RTC Register Addresses (400/500/600/700/800/900 Models) . . ....... 7–23
27 ISDN Direct Address Registers (300 Models) .................... 7–24
28 ISDN Indirect Address Registers (300 Models) . . . ............... 7–24
29 ISDN Directly Addressed Registers (400/500/600/700/800/900
Models) ................................................ 7–26
30 ISDN Indirectly Addressed Registers (400/500/600/700/800/900
Models) ................................................ 7–27
31 TURBOchannel Dual SCSI Address Map ....................... 8–2
32 TURBOchannel Dual SCSI ASIC Register Map . . . ............... 8–3
33 Baud Rate Programming . . . ................................ 9–11
34 SCC Signal Connections .................................... 9–12
35 Dual SCSI Interface: Differences Among Models . . ............... 9–15
36 Data Transfer Error Coverage ............................... 10–3
37 Priority of PAL Entry Points ................................ 10–4
38 System Error/Interrupt Matrix .............................. 10–7
xi