Technical information

Performance

Hysteresis Approximately 0.5 V, positive and negative

Characteristics Single-ended input, 100-K impedance to gnd

Clock output

Signal CLK OV L (clock overﬂow, asserted low)

Output pins J1 pin 5 and CLK OVFL tab

Function Time base selection from an internal

crystal-controlled frequency, an input at ST1, or a

line frequency at BEVNT bus line

Duration Approximately 500 nanoseconds

Line driver TTL-compatible, open collector circuit with a

470- pull-up resistor to +5 V

Maximum source current 5 mA when output is high ( 2.4 V), measuring

from source through load to ground

Maximum sink current 8 mA when output is low (

0.8 V), measuring from

external source voltage through load to output

Schmitt-Trigger 1 output

Signal ST1 OUT L (asserted low)

Output pins J1 pin 2 and ST1 OUT tab

Function External time base input or counter. Input

frequency is a function of the input signal.

Other characteristics Same as clock output

Schmitt-Trigger 2 output

Signal ST2 OUT L (asserted low)

Output pin J1 pin 4

Function Starts counter, sets ST2 ﬂag, and generates an

interrupt (if enabled); causes buffer preset register

(BPR) to be loaded from counter.

Other characteristics Same as clock output

Conﬁguration Information

Power requirements +5 Vdc, 2.2 A (typ); +12 Vdc, 0.013 A (typ)

Power consumption 11.156 W

Bus loads 1.0 ac; 0.3 dc