User Manual

Technical Description

Version 4 4-5 04/02/04

Frequency Synthesizer

The frequency synthesizer is used to stabilize the source for the

carrier (139.3 to 163.3 MHz) phased-locked to stable reference

frequency of 3 MHz, supplied from the reference PLL. Hence, the

carrier frequency will be very stable. The frequency synthesizer is

realized with a single integrated circuit.

The frequency synthesizer divides the reference frequency of 3

MHz from the reference PLL. The amplified feedback of the output

signal from the VCO (139.3 – 163.3 MHz) is divided into the same

frequency as the reference frequency.

Since a number of channels can be used, the frequency

synthesizer is supplied with channel data from CPU. The channel

data consists of two divisors, which are used for the internal

frequency divisions. The divisors correspond to the channel that is

used. By means of the divisors, frequency steps of either 5, 6.25,

or 7.5 KHz are achieved. The CPU sends the divisors in serial form

on a common data line. The data will not be accessible by the

frequency synthesizer until a strobe signal arrives from the CPU. A

clock signal from CPU is used for loading the data. The signals

labeled common data and clock signal are passed through a low-

pass filter in the channel PLL.

The synthesizer detects the difference in phase between the

divided reference frequency and the divided output frequency for

the VCO. If there is a difference between the two signals, an output

voltage will be set high or low in order to change the output

frequency of the VCO. When the phase difference has been

eliminated, the loop has locked and the output frequency from the

VCO is phased-locked to the stable reference frequency. If the

loop cannot be locked an alarm signal is sent to the CPU.

Charge Pump

The Charge Pump circuit charges and discharges a capacitor in the

loop filter to provide the 12V VCO control voltage. Pulses, which

control the charge pump, are fed out of PLL IC, pins R and V.

When both phase detector inputs are in phase, these output signals

are high except for a very short period when both pulses are low in

phase. If the frequency of the f

input to the phase detector is

higher than that of the f

input, the VCO frequency is too low. The

negative-going pulses on the f

output then become much wider

and the f

output stays essentially high. If the frequency of the f

input is greater than f

, the opposite occurs.