User's Manual

Solutions for a Real Time World
ANTHIAS BLE Module
User Manual
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Copyright Unigen Corporation, 2012
Instruction Cycle
The ANTHIS module is the slave and receives commands on DEBUG_MOSI and outputs data on
DEBUG_MISO.
The table below shows the instruction cycle for a SPI transaction.
Table 12: SPI Transactions
1 Reset the SPI interface
Hold DEBUG_CS# high for 2
DEBUG_CLK cycles
2 Write the command word
Take DEBUG_CS# low and clock in the
8-bit command
3 Write the address Clock in the 16-bit address word
4 Write or read data words Clock in or out 16-bit data word(s)
5 Termination Take DEBUG_CS# high
With the exception of reset, DEBUG_CS# must be held low during the transaction. Data on
DEBUG_MOSI is clocked into the Anthias on the rising edge of the clock line DEBUG_CLK. When
reading, Anthias replies to the master on DEBUG_MISO with the data changing on the falling edge
of the DEBUG_CLK. The master provides the clock on DEBUG_CLK. The transaction is terminated
by taking DEBUG_CS# high.
The auto increment operation on the Anthias cuts down on the overhead of sending a command
word and the address of a register for each read or write, especially when large amounts of data
are to be transferred. The auto increment offers increased data transfer efficiency on the Anthias
module. To invoke auto increment, DEBUG_CS# is kept low, which auto increments the address,
while providing an extra 16 clock cycles for each extra word written or read.
Multi-slave Operation
Do not connect the Anthias module in a multi-slave arrangement by simple parallel connection of
slave MISO lines. When Anthias is deselected (DEBUG_CS# = 1), the DEBUG_MISO line does not
float. Instead, Anthias outputs 0 if the processor is running or 1 if it is stopped.