User Manual

Smart Machine Smart Decision
SIM7100_Hardware_Design_V1.02 2015-06-16
Figure 24: EXT CODEC to MODULE timing
Figure 25: MODULE to EXT CODEC timing
Table 15: PCM Timing parameters
Parameter Description Min. Typ. Max. Unit
T(sync) PCM_SYNC cycle time – 125 – μs
T(synch) PCM_SYNC high level time –
488
– ns
T(syncl) PCM_SYNC low level time – 124.5 – μs
T(clk) PCM_CLK cycle time – 488 – ns
T(clkh) PCM_CLK high level time – 244 – ns
T(clkl) PCM_CLK low level time – 244 – ns
T(susync)
PCM_SYNC setup time high before falling edge of
PCM_CLK
– 122 – ns
T(hsync)
PCM_SYNC hold time after falling edge of
PCM_CLK
– 366 – ns
T(sudin)
PCM_IN setup time before falling edge of
PCM_CLK
60 – – ns
T(hdin) PCM_IN hold time after falling edge of PCM_CLK 60 – – ns
T(pdout) Delay from PCM_CLK rising to PCM_OUT valid – – 60 ns
T(zdout)
Delay from PCM_CLK falling to PCM_OUT
HIGH-Z
– – 60 ns