Datasheet

Philips Semiconductors Linear Products Product specification
NE502010-Bit µP-compatible D/A converter
August 31, 1994
765
Figure 13. Bipolar Output
DAC
CURRENT
FROM
CURRENT
SWITCHES
OUTPUT
AMP
To R-2R Ladder
DAC
AMP
BIPOLAR
OFFSET (18)
JUMPER FOR
BIPOLAR OPERATION
SUM
NODE (22)
(16)
+
–
–
+
5k
5k
(17)
V
REF
IN
I
D
(I
D
I
REF
)
V
CC
I
REF
5k
Reference Interface
The NE5020 contains an internal bandgap voltage reference which
is designed to have a very low temperature coefficient and excellent
long-term stability characteristics.
The internal bandgap reference (1.23V) is buffered and amplified to
provide the 5V reference output. Providing a V
REF ADJ
(Pin 14)
allows trimming of the reference output. Utilization of the adjust
circuit shown in Figure 15 performs not only V
REF
adjustment, but
also full-scale output adjust. Notice that the V
REF ADJ
pin is
essentially the sum node of an op amp and is sensitive to excessive
node capacitance. Any capacitance on the node can be minimized
by placing the external resistors as close as possible to the V
REF
ADJ
pin and observing good layout
practices.
The V
REF OUT
node can drive loads greater than the DAC V
REF
input requirements and can be used as an excellent system voltage
reference. However, to minimize load effects on the DAC system
accuracy, it is recommended that a buffer amplifier be used.
Input Amplifier
The DAC reference amplifier is a high gain internally-compensated
op amp used to convert the input reference voltage to a precision
bias current for the DAC ladder network.
The Block Diagram details the input reference amplifier and current
ladder. The voltage-to-current converter of the DAC amp will
generate a 1mA reference current through QR with a 5V V
REF
. This
current sets the input bias to the ladder network. Data bit 9
(DB9)(Q9), when turned on, will mirror this current and will
contribute 1mA to the output. DB8 (Q8) will contribute 1/2 of that
value or 0.5mA, and so on. These current values act as current
sinks and will add at the sum node to produce a DAC ladder to sum
node function of:
I
OUT

2V
REF
R
REF

DB9
2

DB8
4

DB7
8

DB6
16

DB5
32

DB4
64

DB3
128

DB2
256

DB1
512

DB0
1024
Because of the fixed internal compensation of the reference amp,
the slew rate is limited to typically 0.7V/µs and source impedance at
the V
REF INPUT
greater than 5kΩ should be avoided to maintain
stability.
The –V
REF INPUT
pin is uncommitted to allow utilization of negative
polarity reference voltages. In this mode +V
REF INPUT
is grounded
and the negative reference is tied directly to the –V
REF INPUT
contains a 5kΩ resistor that matches a like resistor in the +V
REF
INPUT
to reduce voltage offset caused by op amp input bias currents.
Output Amplifier and Interface
The NE5020 provides an on-chip output op amp to eliminate the
need for additional external active circuits. Its two-stage design with
feed-forward compensation allows it to slew at 15V/µs and settle to
within ±1/2LSB in 5µs. These times are typical when driving the
rated loads of R
L
≥ 5k and C
L
50pF with recommended values of
C
FF
= 1nF and C
FB
= 30pF. Typical input offset voltages of 5mV
and 50kΩ open-loop gain insure that an accurate current-to-voltage
conversion is performed when using the on-chip R
FB
resistor. R
FB
is matched to R
REF
and R
BIP
to maintain accurate voltage gain over
operating conditions. The diode shown from ground to sum node
prevents the DAC current switches from saturating the op amp
during large signal transitions which would otherwise increase the
settling time.
The output op amp also incorporates output short circuit protection
for both positive and negative excursions. During this fault condition
I
OUT
will limit at ±15mA typical. Recovery from this condition to
rated accuracy will be determined by duration of short-circuit and die
temperature stabilization.