Datasheet

Philips Semiconductors Linear Products Product specification
NE502010-Bit µP-compatible D/A converter
August 31, 1994
760
DC ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
Min Typ Max
UNIT
V
ZS
Zero-scale output Unipolar mode, V
REF
=5.000V, all bits low, T
A
=25°C -30 +30 mV
I
OS
Output short-circuit current T
A
=25°C
V
OUT
=0V
±15 ±40 mA
PSR+
(OUT)
Output power supply rejection (+) V-=-15V, 13.5V≤V+≤16.5V, external
V
REF IN
=5.000V
0.001 0.01 %FS/
%VS
PSR-
(OUT)
Output power supply rejection (-) V+=15V, -13.5V≤V-≤-16.5V, external
V
REF IN
=5.000V
0.001 0.01 %FS/
%VS
TC
FS
Full-scale temperature coefficient V
REF IN
=5.000V 20 ppmFS
/°C
TC
ZS
Zero-scale temperature coefficient 5 ppmFS/°C
I
REF
2
Reference output current 3 mA
I
REF SC
Reference short circuit current T
A
=25°C
V
REF OUT
=0V
15 30 mA
PSR+
REF
Reference power supply rejection
(+)
V-=-15V, 13.5V≤V+≤16.5V, I
REF
=1.0mA .003 .01 %VR/
%VS
PSR-
REF
Reference power supply rejection
(-)
V+=15V, -13.5V≤V-≤16.5V, .003 .01 %VR/
%VS
V
REF
Reference voltage I
REF
=1.0mA, T
A
=25°C 4.9 5.0 5.25 V
TC
REF
Reference voltage temperature co-
efficient
I
REF
=1.0mA 60 ppm/°C
Z
IN
DAC V
REF IN
input impedance I
REF
=1.0mA 5.0 kΩ
I
CC
+ Positive supply current V
CC
+=15V 7 14 mA
I
CC
- Negative supply current V
CC
-=-15V -10 -15 mA
P
D
Power dissipation I
REF
=1.0mA, V
CC
=±15V 255 435 mW
NOTES:
1. Refer to Figure 1.
2. For I
REF OUT
greater than 3mA, an external buffer is required.
AC ELECTRICAL CHARACTERISTICS
1
V
CC
= +15V, T
A
= 25°C.
SYMBOL
PARAMETER
TO
FROM
TEST CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
TO
FROM
TEST CONDITIONS
Min Typ Max
UNIT
t
SLH
Settling time ±1/2LSB Input All bits low-to-high
2
5 µs
t
SHL
Settling time ±1/2LSB Input All bits high-to-low
3
5 µs
t
PLH
Propagation delay Output Input All bits switched low-to-high
2
30 ns
t
PHL
Propagation delay Output Input All bits switched high-to-low
3
150 ns
t
PLSB
Propagation delay Output Input 1 LSB change
2,3
150 ns
t
PLH
Propagation delay Output LE Low-to-high transition
4
300 ns
t
PHL
Propagation delay Output LE High-to-low transition
5
150 ns
t
S
Set-up time LE Input
1,6
100 ns
t
H
Hold time Input LE
1,6
50 ns
t
PW
Latch enable pulse width
1,6
150 ns
NOTES:
1. Refer to Figure 2.
2. See Figure 5.
3. See Figure 6.
4. See Figure 7.
5. See Figure 8.
6. See Figure 9.