Information

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Copyright LZE GmbH 2021
Package and Circuit Connection
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3.2
Pins
Pin
Symbol
Type
Description
A1
MISO
DO_T
Master in / Slave out (SPI interface data output)
A2
CLK
DIO
Clock input / output. Must be connected to VSS if internal
clock is used
A3
B3
VSS1
S
Ground (0V) Note: both VSS1 and VSS2 must be connected
A4
SCE
DI_ST
Test pin, must be connected to VSS in normal operation
A5
LOPOW
R
DI_ST
Shutdown & Reset input.
Connect to VSS in normal operation
A6
CS_N
DI_ST
Chip select (active low)
B2
MOSI
DI_ST
Master out / Slave in (SPI interface data input)
B4
C5
VSS2
S
Ground (0V) Note: both VSS1 and VSS2 must be connected
B5
SCK
DI_ST
SPI clock input
C1
READY
DO_T
Measurement ready signal
C2
RESET_
N
DI_PU
Reset input (active low)
C3
LOCK_N
DI_ST
Test pin, must be connected to VSS in normal operation
C4
VDD
S
Positive supply voltage ( 3.3 V)
C6
PWM
DO
Linearized angle output in PWM mode.
Pin/Bump list
DIO digital input & output
DI_ST digital Schmitt-Trigger input
DI_PU digital input with pull-up
DO digital output
DO_T digital output /tri-state
S supply pin
Notes:
- Pins LOCK_N and SCE are test pins for factory testing. They must be connected to VSS in
normal operation to prevent accidental enabling of a test mode.
- Output READY is set high when a measurement cycle is completed and the results in the output
registers are valid. It is cleared by reading data from address 0122h.
- CLK allows to monitor the internal clock or to apply an external clock.
- Output MISO is only activated when CS_N is low. It is in high impedance state otherwise, this
allows for parallel operation of multiple ICs.
- CS_N is active low and activates data transmission. If only a single device is used, CS_N may
remain low for several commands, for example while reading the output registers.