Data Sheet

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Copyright LZE GmbH 2021
Additional Features
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Please note:
It is strongly recommended to use an impedance controlled digital signal line with source resistor (e.g.
R
ser
as shown) for the clock wire.
The reset sequence always uses the internal clock, even if 0x0440 is written to 0x0004 in the EEPROM.
For synchronization reasons the external clock will not be used until the first SCK edge. This edge must
not occur before the end of the reset cycle and does not need a CS_N=0.
Do not connect more than 16 (32) ICs to one CLK output if a 100 Ω (50 Ω) series resistor is used.
Clock generation by one FH3D02 with CLK output
Write value 0x0840 to register 0x0004 of the CLK output device. Write value 0x0440 to register 0x0004 of
all CLK input devices.
Example for configuration with several FH3D02 devices and IC1 as clock source.
Please note:
Do not connect more than 16 (32) ICs to one CLK output if a 100 Ω (50 Ω) series resistor is used.
The reset sequence always uses the internal clock. For synchronization reasons the external
clock will not be used until the first SCK edge. This edge must not occur before the end of the
reset cycle and does not need a CS_N=0.
IC n
(CLK i n)
IC 2
(CLK i n)
IC 1
(CLK out )
µC
[SP I ]
CLK
[SP I ][SP I ]
CLK CLK
[SP I ]
[SP I ] I/O