Data Sheet

Seite 36 von 44
Copyright LZE GmbH 2021
Additional Features
Eine gemeinsame Initiative von
Parameter
Symbol
Min
Typ
Max
Unit
Note
Clock frequency
f
clkExt
7.5
8
MHz
Edge rise time
t
rise
ns
0.3 V to 2.7 V
Edge fall time
t
fall
ns
2.7 V to 0.3 V
Duty cycle
tc
duty
49
51
%
External clock
characteristics
The clock behavior can be set by setting bits D10 and D11 in SPI register 0x0004.
Bit
Symbol
Default
Value
Description
D15 (MSB)
– D12
r
0
(Reserved. Always set to default state)
D11
OscOut
0
“Oscillator Output Enable”
0: oscillator output disabled, pin CLK is high
impedance
1: oscillator output enabled, pin CLK is active
D10
OscPD
0
“Oscillator Power Down”
0: internal oscillator is enabled
1: internal oscillator is disabled, clock signal at pin
CLK is used as system clock
D9 – D7
r
0
(Reserved. Always set to default state)
D6
BiasOn
1
“Internal Bias References Enable”
This bit must not be set to 0.
D5
– D0 (LSB)
r
0
(Reserved. Always set to default state)
0x0004 Bits
Two different modes of operation are possible and described in the following sections.
Clock signal generated by external source
Write value 0x0440 to register 0x0004 of all devices. Apply the external clock signal to pin CLK.
Example for configuration with several FH3D02 devices and one master controller as clock source.
IC n
(CLK i n)
IC 2
(CLK i n)
IC 1
(CLK i n)
µC
[SP I ]
CLK
[SP I ][SP I ]
CLK CLK
[SP I ]
R
ser
Output
[SP I ] I/O