Data Sheet
Table Of Contents
- 1 FH3D02 Overview
- 2 Characteristics
- 3 Package and Circuit Connection
- 4 SPI Communication
- 5 List of Registers
- 5.1 Measurement Register Contents
- 5.1.1 0x000B (read/write) – Measurement Control
- 5.1.2 0x000E (read/write) – Measurement Start
- 5.1.3 0x0107 (read only) – Status Register
- 5.1.4 0x0110 (read only) – Temperature Sensor
- 5.1.5 0x0111 (read only) – Bi0 Magnetic Field
- 5.1.6 0x0112 (read only) – Bi1 Magnetic Field
- 5.1.7 0x0113 (read only) – Bj0 Magnetic Field
- 5.1.8 0x0114 (read only) – Bj1 Magnetic Field
- 5.1.9 0x0120 (read only) – Magnetic Field Magnitude
- 5.1.10 0x0121 (read only) – Magnetic Field Angle
- 5.1.11 0x0122 (read only) – Linearized Angle / Bz1 Field (Special Function Mode)
- 5.1.12 0x0124 (read only) – Bz0 Magnetic Field (Special Function Mode)
- 5.2 Result Register Overview
- 5.1 Measurement Register Contents
- 6 Measurement Modes
- 6.1 Single Magnetic Probe
- 6.2 Dual Magnetic Probe
- 6.3 Linear Position or Off-Axis Angle Sensor (Absolute Field Values, Magnet On-Top)
- 6.4 Linear Position or Off-Axis Angle Sensor (Gradient Field Values, Magnet On-Top)
- 6.5 Linear Position or Off-Axis Angle Sensor (Absolute Field Values, Magnet At-The-Side)
- 6.6 Linear Position or Off-Axis Angle Sensor (Gradient Field Values, Magnet At-The-Side)
- 7 Additional Features
- 8 LZE GmbH
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Package and Circuit Connection
3.2
Pins
Pin
Symbol
Type
Description
A1
MISO
DO_T
Master in / Slave out (SPI interface data output)
A2
CLK
DIO
Clock input / output. Must be connected to VSS if internal
clock is used
A3
B3
VSS1
S
Ground (0V) Note: both VSS1 and VSS2 must be connected
A4
SCE
DI_ST
Test pin, must be connected to VSS in normal operation
A5
LOPOW
R
DI_ST
Shutdown & Reset input.
Connect to VSS in normal operation
A6
CS_N
DI_ST
Chip select (active low)
B2
MOSI
DI_ST
Master out / Slave in (SPI interface data input)
B4
C5
VSS2
S
Ground (0V) Note: both VSS1 and VSS2 must be connected
B5
SCK
DI_ST
SPI clock input
C1
READY
DO_T
Measurement ready signal
C2
RESET_
N
DI_PU
Reset input (active low)
C3
LOCK_N
DI_ST
Test pin, must be connected to VSS in normal operation
C4
VDD
S
Positive supply voltage ( 3.3 V)
C6
PWM
DO
Linearized angle output in PWM mode.
Pin/Bump list
DIO digital input & output
DI_ST digital Schmitt-Trigger input
DI_PU digital input with pull-up
DO digital output
DO_T digital output /tri-state
S supply pin
Notes:
- Pins LOCK_N and SCE are test pins for factory testing. They must be connected to VSS in
normal operation to prevent accidental enabling of a test mode.
- Output READY is set high when a measurement cycle is completed and the results in the output
registers are valid. It is cleared by reading data from address 0122h.
- CLK allows to monitor the internal clock or to apply an external clock. Refer to chapter 7.6 for
further information.
- Output MISO is only activated when CS_N is low. It is in high impedance state otherwise, this
allows for parallel operation of multiple ICs.
- CS_N is active low and activates data transmission. If only a single device is used, CS_N may
remain low for several commands, for example while reading the output registers.