Data Sheet

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Additional Features
EEPROM Clock Settings
If the oscillator settings from SPI register 0x0004 are stored in the EEPROM attention should be paid to
the startup procedure:
During the boot procedure an untrimmed internal clock frequency is used. After a certain time t
res
the
rising READY indicates that the boot procedure is finished and communication on the SPI can
commence.
During an additional time t
clk_init
the internal clock frequency remains at its initial raw value and will change
to the nominal f
clk
afterwards without external indication.
The internal (raw or trimmed) clock will be used until a first SCK rising edge. Any setting of bits OscOut
and OscPD will not take effect until the first SCK rising edge. Only then the CLK output will be active or
an external clock source will be used as system clock.
Please note:
A reset can be triggered externally on RESET_N or internally by the VDD-dependent power-on-
reset.
The READY behavior depends on bit settings Rdy2hZ (see chapter 5.1.1).
For f
clk
refer to table “System clock frequency” above.
For t
res
refer to t
res1
in chapter 5.1.2.
Parameter
Symbol
Min
Typ
Max
Unit
Note
Raw clock
frequency
f
init
0.85 2 7.3
MHz
Initial clock delay
time
t
clk_init
4.5 16 35
µs
Boot procedure
parameters