Data Sheet
Table Of Contents
- 1 FH3D02 Overview
- 2 Characteristics
- 3 Package and Circuit Connection
- 4 SPI Communication
- 5 List of Registers
- 5.1 Measurement Register Contents
- 5.1.1 0x000B (read/write) – Measurement Control
- 5.1.2 0x000E (read/write) – Measurement Start
- 5.1.3 0x0107 (read only) – Status Register
- 5.1.4 0x0110 (read only) – Temperature Sensor
- 5.1.5 0x0111 (read only) – Bi0 Magnetic Field
- 5.1.6 0x0112 (read only) – Bi1 Magnetic Field
- 5.1.7 0x0113 (read only) – Bj0 Magnetic Field
- 5.1.8 0x0114 (read only) – Bj1 Magnetic Field
- 5.1.9 0x0120 (read only) – Magnetic Field Magnitude
- 5.1.10 0x0121 (read only) – Magnetic Field Angle
- 5.1.11 0x0122 (read only) – Linearized Angle / Bz1 Field (Special Function Mode)
- 5.1.12 0x0124 (read only) – Bz0 Magnetic Field (Special Function Mode)
- 5.2 Result Register Overview
- 5.1 Measurement Register Contents
- 6 Measurement Modes
- 6.1 Single Magnetic Probe
- 6.2 Dual Magnetic Probe
- 6.3 Linear Position or Off-Axis Angle Sensor (Absolute Field Values, Magnet On-Top)
- 6.4 Linear Position or Off-Axis Angle Sensor (Gradient Field Values, Magnet On-Top)
- 6.5 Linear Position or Off-Axis Angle Sensor (Absolute Field Values, Magnet At-The-Side)
- 6.6 Linear Position or Off-Axis Angle Sensor (Gradient Field Values, Magnet At-The-Side)
- 7 Additional Features
- 8 LZE GmbH
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Additional Features
7.5 Parallel Operation of Multiple Devices
For several applications it might be necessary to use several devices with only one master controller.
The simplest way to communicate with several ICs for combined operation is to use separate CS_N wires
for every device. Communication with a device is only possible while CS_N is low. Then the output MISO
is active, otherwise it is high impedance (see also 4.1).
Please note:
If READY is wired in parallel it must be set to high-Z mode (Rdy2hZ = 1). Then the READY signal
is active only if the chip is selected.
IC n IC 2 IC 1
µC
M O SIM ISOSC K
CS_N
REA D Y
SC KSC K M ISOM ISO M O SIM O SI
CS_N
CS_N
REA D Y REA D Y
REA D Y
SC K
M ISO
M O SI
CS_N 2
CS_N n
CS_N 1
Example for configuration with several FH3D02 devices and one master controller in chip select mode.
7.6 CLK Input/Output
The system clock of the FH3D02 is generated by an internal RC oscillator if it is used in standard
configuration. Due to process variations the clock frequency exhibits certain spread. The characteristics
are noted in the following table.
Parameter
Symbol
Min
Typ
Max
Unit
Note
System clock
frequency
f
clk
7.5 8
MHz
System clock
frequency
Several devices in a combined setup can be started synchronously by group addressing (see 7.5) but will
complete their measurement cycles at different points in time. For absolutely synchronous measurements
a common clock can be used. By disabling the internal oscillator the signal edges at pin CLK will be used
as system clock. See the following table for the necessary characteristics of this clock signal.