Data Sheet

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Additional Features
7.4 PWM Output
From the measured and linearized angle in SPI register 0x0122 a PWM signal can be generated. The
base frequency of the PWM is the system clock frequency of typ. 8 MHz. Hence one PWM digit always
corresponds to approx. 125 ns.
The PWM signal is available at pin PWM. If one of the error flags MgnLost or CalcErr occurs the PWM
output will be disabled with PWM remaining at the current level (high or low). In that way it is ensured that
no false falling edge is generated and an external controller can capture the error event by a timeout
counter.
In PWM mode both flags can also be made available at pins READY (MagLost) and MISO (CalcErr) by
setting PWMflags in register 000Bh to 1.
The PWM duty cycle can be limited to a low and high threshold. Even if the measured and linearized
angle exceeds these limits, the duty cycle will clip there. The low limit can be set to any value between
0% and 50%, the high limit to any value between 50% and 100%, both with a resolution of 6 bit.
The settings and activation of the PWM output are defined by the 16-bit word at EEPROM address
0x00D.
Bit
Symbol
Description
D15 (MSB)
D10
PWMLimitHi
“PWM Limit High”
Limits the PWM duty cycle to the maximum value
󰇡
50
64
+ 50󰇢%
D9 D4
PWMLimitLo
“PWM Limit Low”
Limits the PWM duty
cycle to the minimum value
󰇡
50
64
󰇢%
D3
PWMEn
“PWM Enable”
Enables the PWM output.
D2 D0
(LSB)
PWMPreScale
PWM PreScale
Defines the PWM frequency and resolution. Refer to the
following table for further information.
0x00D Bits
(PWM setting)
The PWM resolution and update frequency are both set by the 3 bits of PWMPreScale which shift the 16
bit wide angle value by 0 to 7 digits. The following table shows the effect of this setting.
PWMPreScale
PWM Resolution
Min. frequency f
PWM
Max. frequency f
PWM
0b000
16 bit
0.122 kHz
0b001
15 bit
0.244 kHz
0b010
14 bit
0.49 kHz
0b011
13 bit
0.98 kHz
0b100
12 bit
1.95 kHz
0b101
11 bit
3.91 kHz
0b110
10 bit
7.81 kHz
0b111
9 bit
15.63 kHz
PWM frequency