Data Sheet

Table Of Contents
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Additional Features
7.2 EEPROM Access
The internal 512 x 16bit EEPROM is a non-volatile memory which holds initialization and calibration data
and the definition of internal measurement sequences. Certain address ranges of the EEPROM are
accessible and can be modified. Others must not or can not be modified.
Read and write access is performed via the SPI registers 0x0030 and 0x0031. The desired address is
written to register 0030h and the stored bits can be read from register 0031h or written to it. The internal
write cycle requires 10ms before the data is permanently stored. After completion the status bit EEDone
in register 0107h is set to 1. This write cycle must not be interrupted by power down, reset or VDD power
loss.
Symbol
Description
EEAddr
EEPROM address
EEData
EEPROM data
Status flags
SPI registers for
EEPROM access
The following timing diagram shows a typical EEPROM write cycle. After setting EEAdr and writing
EEData the internal write cycle is started. After 10 ms the internal EEDone signal is set and bit 0 in status
register 0x0107 will be logical 1. Not before this the EEPROM content can be read and verified by reading
from register 0x0031.
Timing diagram of an EEPROM write cycle. Use CS_N and SCK according to SPI protocol (section 4.1). Values shown as 0x****
depend on settings and EEPROM content. I
EEWrite
is typically I
standby
+ 100 µA.
Please note:
By altering the EEPROM content holding calibration data and measurement sequence definitions
the functionality of the device is altered and malfunctions will occur. An access restriction as
described in chapter 7.3 can prevent unintended modifications and is strongly recommended.
Do not access the EEPROM during measurements. Read and write access is only allowed during
standby. The guaranteed number of write cycles to the EEPROM is 40,000, independent from the
chosen address.