Data Sheet

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Additional Fe
atures
7
Additional Features
7.1 Low Power Mode
For low power applications the FH3D02 can be set to a low power mode. In this mode all analog
components are turned off and the oscillator and digital components are stopped. The low power mode is
enabled by logical levels at pin LOPOWR. A logical rise signal will immediately enable the low power
mode. Any measurement will be interrupted and the SPI will not return any data. After a logical fall signal
at LOPOWR a reset cycle will be performed and the IC will enter its initial condition. All necessary SPI
register settings must be rewritten as they return to their initial states during the reset.
Please note:
The reset cycle at leaving the low power mode requires the regular reset wait time t
res1
before
starting the SPI communication (see chapter 5.1.2).
State
Current consumption
Note
Low power
mode
IDD
lowpower
All internal components are switched
off.
Normal
operation
[depending on
operation mode]
The SPI register content is reset when
returning to normal operation.
Low power mode
information