Data Sheet
Analog Integrated Circuit Device Data
8 Freescale Semiconductor
33926
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics
Characteristics noted under conditions 5.0 V V
PWR
28 V, - 40 C T
A
125 C, GND = 0 V, unless otherwise noted. Typical
values noted reflect the approximate parameter means at T
A
= 25 °C under nominal conditions, unless otherwise noted.
Symbol Characteristic Min Typ Max Unit Notes
POWER INPUTS (VPWR)
V
PWR(SS)
V
PWR(T)
Operating Voltage Range
Steady-state
Transient (t < 500 ms)
5.0
–
–
–
28
40
V
(10)
(11)
I
PWR(SLEEP)
Sleep State Supply Current
EN, D2, INV, SLEW = Logic [0], IN1, IN2, D1 = Logic [1], and
I
OUT
= 0 A
– – 50
A
(12)
I
PWR(STANDBY)
Standby Supply Current (Part Enabled)
I
OUT
= 0 A, V
EN
= 5.0 V
– – 20
mA
V
UVLO(ACTIVE)
V
UVLO(INACTIVE)
V
UVLO(HYS)
Undervoltage Lockout Thresholds
V
PWR(FALLING)
V
PWR(RISING)
Hysteresis
4.15
–
150
–
–
200
–
5.0
350
V
V
mV
CHARGE PUMP
V
CP
- V
PWR
Charge Pump Voltage (CP Capacitor = 33 nF)
V
PWR
= 5.0 V
V
PWR
= 28 V
3.5
–
–
–
–
12
V
CONTROL INPUTS
V
I
Operating Input Voltage (EN, IN1, IN2, D1, D2, INV, SLEW)
– – 5.5 V
V
IH
V
IL
V
HYS
Input Voltage (IN1, IN2, D1, D2, INV, SLEW)
Logic Threshold HIGH
Logic Threshold LOW
Hysteresis
2.0
–
250
–
–
400
–
1.0
–
V
V
mV
(13)
V
TH
Input Voltage (EN) Threshold
1.0 – 2.0 V
I
IN
Logic Input Currents, VPWR = 5.0 V
Inputs EN, D2, INV, SLEW (internal pull-downs), V
IH
= 5.0 V
Inputs IN1, IN2, D1 (internal pull-ups), VIL = 0 V
20
-200
80
-80
200
-20
A
Notes
10. Device specifications are characterized over the range of 8.0 V V
PWR
28 V. Continuous operation above 28 V may degrade device
reliability. Device is operational down to 5.0
V, but below 8.0 V the output resistance may increase by 50 percent.
11. Device will survive the transient overvoltage indicated for a maximum duration of 500 ms. Transient not to be repeated more than once
every 10 seconds.
12. I
PWR(SLEEP)
is with Sleep mode activated and EN, D2, INV, SLEW = logic [0], and IN1, IN2, D1 = logic [1] or with these inputs left floating.
13. SLEW input voltage hysteresis is guaranteed by design.