Datasheet

7-742
CD4016BMS
Chip Dimensions and Pad Layout
FIGURE 20. PROPAGATION DELAY TIME SIGNAL INPUT (VIS)
TO SIGNAL OUTPUT (VOS)
FIGURE 21. MAXIMUM CONTROL-INPUT REPETITION RATE
FIGURE 22. SWITCH THRESHOLD VOLTAGE FIGURE 23. CAPACITANCE CIOS AND COS
FIGURE 24. TURN-ON PROPAGATION DELAY CONTROL INPUT
CD4016BMS
+10V
0
VDD
V
os
V
is
tr = tf = 20ns
ALL UNUSED TERMINALS
ARE CONNECTED TO VSS
VSS
200KΩ
CL
VDD
0
VDD
V
os
V
is
tr = tf = 20ns
ALL UNUSED TERMINALS
ARE CONNECTED TO VSS
VSS
CL
= VDD
RL = 10KΩ
VC
REP
RATE
tr = tf = 20ns
VC
CD4016BMS
VC
V
os
SWITCH THRESHOLD VOLTAGE IS DEFINED AS THE VOLTAGE
APPLIED TO A TRANSMISSION GATE CONTROL WHICH CAUSES
10µA OF TRANSMISSION GATE CURRENT
V
is
= VDD
±
VSS
I
(13)
(1)
I = 10µA
CD4016BMS
MEASURED ON BOONTON CAPACITANCE
BRIDGE MODEL 75A (1MHz)
VC = -5V
VSS = -5V
VDD = +5V
CIOS
V
is
C
is
V
os
C
os
ALL UNUSED TERMINALS
ARE CONNECTED TO VSS
VDD
0
VDD
V
os
V
is
tr = tf = 20ns
ALL UNUSED TERMINALS
ARE CONNECTED TO VSS
VSS
CL
= VDD OR VSS
RL
VC
VSS
VDD
50%
10%
10%
VC
V
os
V
os
tPZH
tPZL
RL TO VSS
V
is
TO VDD
RL TO VDD
V
is
TO VSS
CD4016BMS
Dimensions in parentheses are in millimeters
and are derived from the basic inch dimensions
as indicated. Grid graduations are in mils (10
-3
inch)
METALLIZATION: Thickness: 11kÅ − 14kÅ, AL.
PASSIVATION: 10.4kÅ - 15.6kÅ, Silane
BOND PADS: 0.004 inches X 0.004 inches MIN
DIE THICKNESS: 0.0198 inches - 0.0218 i