User Manual

MPU-6000/MPU-6050 Register Map and
Descriptions
Document Number: RM-MPU-6000A-00
Revision: 4.2
Release Date: 08/19/2013
6 of 46
3 Register Map
The register map for the MPU-60X0 is listed below.
Addr
(Hex)
Addr
(Dec.)
Register Name
Serial
I/F
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
0D
13
SELF_TEST_X
R/W
XA_TEST[4-2]
XG_TEST[4-0]
0E
14
SELF_TEST_Y
R/W
YA_TEST[4-2]
YG_TEST[4-0]
0F
15
SELF_TEST_Z
R/W
ZA_TEST[4-2]
ZG_TEST[4-0]
10
16
SELF_TEST_A
R/W
RESERVED
XA_TEST[1-0]
YA_TEST[1-0]
ZA_TEST[1-0]
19
25
SMPLRT_DIV
R/W
SMPLRT_DIV[7:0]
1A
26
CONFIG
R/W
-
-
EXT_SYNC_SET[2:0]
DLPF_CFG[2:0]
1B
27
GYRO_CONFIG
R/W
-
-
-
FS_SEL [1:0]
-
-
-
1C
28
ACCEL_CONFIG
R/W
XA_ST
YA_ST
ZA_ST
AFS_SEL[1:0]
23
35
FIFO_EN
R/W
TEMP
_FIFO_EN
XG
_FIFO_EN
YG
_FIFO_EN
ZG
_FIFO_EN
ACCEL
_FIFO_EN
SLV2
_FIFO_EN
SLV1
_FIFO_EN
SLV0
_FIFO_EN
24
36
I2C_MST_CTRL
R/W
MULT
_MST_EN
WAIT
_FOR_ES
SLV_3
_FIFO_EN
I2C_MST
_P_NSR
I2C_MST_CLK[3:0]
25
37
I2C_SLV0_ADDR
R/W
I2C_SLV0
_RW
I2C_SLV0_ADDR[6:0]
26
38
I2C_SLV0_REG
R/W
I2C_SLV0_REG[7:0]
27
39
I2C_SLV0_CTRL
R/W
I2C_SLV0
_EN
I2C_SLV0
_BYTE_SW
I2C_SLV0
_REG_DIS
I2C_SLV0
_GRP
I2C_SLV0_LEN[3:0]
28
40
I2C_SLV1_ADDR
R/W
I2C_SLV1
_RW
I2C_SLV1_ADDR[6:0]
29
41
I2C_SLV1_REG
R/W
I2C_SLV1_REG[7:0]
2A
42
I2C_SLV1_CTRL
R/W
I2C_SLV1
_EN
I2C_SLV1
_BYTE_SW
I2C_SLV1
_REG_DIS
I2C_SLV1
_GRP
I2C_SLV1_LEN[3:0]
2B
43
I2C_SLV2_ADDR
R/W
I2C_SLV2
_RW
I2C_SLV2_ADDR[6:0]
2C
44
I2C_SLV2_REG
R/W
I2C_SLV2_REG[7:0]
2D
45
I2C_SLV2_CTRL
R/W
I2C_SLV2
_EN
I2C_SLV2
_BYTE_SW
I2C_SLV2
_REG_DIS
I2C_SLV2
_GRP
I2C_SLV2_LEN[3:0]
2E
46
I2C_SLV3_ADDR
R/W
I2C_SLV3
_RW
I2C_SLV3_ADDR[6:0]
2F
47
I2C_SLV3_REG
R/W
I2C_SLV3_REG[7:0]
30
48
I2C_SLV3_CTRL
R/W
I2C_SLV3
_EN
I2C_SLV3
_BYTE_SW
I2C_SLV3
_REG_DIS
I2C_SLV3
_GRP
I2C_SLV3_LEN[3:0]
31
49
I2C_SLV4_ADDR
R/W
I2C_SLV4
_RW
I2C_SLV4_ADDR[6:0]
32
50
I2C_SLV4_REG
R/W
I2C_SLV4_REG[7:0]
33
51
I2C_SLV4_DO
R/W
I2C_SLV4_DO[7:0]
34
52
I2C_SLV4_CTRL
R/W
I2C_SLV4
_EN
I2C_SLV4
_INT_EN
I2C_SLV4
_REG_DIS
I2C_MST_DLY[4:0]
35
53
I2C_SLV4_DI
R
I2C_SLV4_DI[7:0]
36
54
I2C_MST_STATUS
R
PASS_
THROUGH
I2C_SLV4
_DONE
I2C_LOST
_ARB
I2C_SLV4
_NACK
I2C_SLV3
_NACK
I2C_SLV2
_NACK
I2C_SLV1
_NACK
I2C_SLV0
_NACK
37
55
INT_PIN_CFG
R/W
INT_LEVEL
INT_OPEN
LATCH
_INT_EN
INT_RD
_CLEAR
FSYNC_
INT_LEVEL
FSYNC
_INT_EN
I2C
_BYPASS
_EN
-
38
56
INT_ENABLE
R/W
-
-
-
FIFO
_OFLOW
_EN
I2C_MST
_INT_EN
-
-
DATA
_RDY_EN
3A
58
INT_STATUS
R
-
-
-
FIFO
_OFLOW
_INT
I2C_MST
_INT
-
-
DATA
_RDY_INT