User Manual

MPU-6000/MPU-6050 Register Map and

Descriptions

Document Number: RM-MPU-6000A-00

Revision: 4.2

Release Date: 08/19/2013

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4.16 Register 58 – Interrupt Status

INT_STATUS

Type: Read Only

(Hex)

(Decimal)

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

FIFO

_OFLOW

_INT

I2C_MST

_INT

DATA

_RDY_INT

Description:

This register shows the interrupt status of each interrupt generation source. Each bit will clear after

the register is read.

For information regarding the corresponding interrupt enable bits, please refer to Register 56.

For a list of I

C Master interrupts, please refer to Register 54.

Bits 2 and 1 are reserved.

Parameters:

FIFO_OFLOW_INT This bit automatically sets to 1 when a FIFO buffer overflow interrupt has

been generated.

The bit clears to 0 after the register has been read.

I2C_MST_INT This bit automatically sets to 1 when an I

C Master interrupt has been

generated. For a list of I

C Master interrupts, please refer to Register 54.

The bit clears to 0 after the register has been read.

DATA_RDY_INT This bit automatically sets to 1 when a Data Ready interrupt is generated.

The bit clears to 0 after the register has been read.