User Manual

MPU-6000/MPU-6050 Register Map and
Descriptions
Document Number: RM-MPU-6000A-00
Revision: 4.2
Release Date: 08/19/2013
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4.3 Register 26 – Configuration
CONFIG
Type: Read/Write
Register
(Hex)
Register
(Decimal)
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
1A
26
-
-
EXT_SYNC_SET[2:0]
DLPF_CFG[2:0]
Description:
This register configures the external Frame Synchronization (FSYNC) pin sampling and the Digital
Low Pass Filter (DLPF) setting for both the gyroscopes and accelerometers.
An external signal connected to the FSYNC pin can be sampled by configuring EXT_SYNC_SET.
Signal changes to the FSYNC pin are latched so that short strobes may be captured. The latched
FSYNC signal will be sampled at the Sampling Rate, as defined in register 25. After sampling, the
latch will reset to the current FSYNC signal state.
The sampled value will be reported in place of the least significant bit in a sensor data register
determined by the value of EXT_SYNC_SET according to the following table.
EXT_SYNC_SET
FSYNC Bit Location
0
Input disabled
1
TEMP_OUT_L[0]
2
GYRO_XOUT_L[0]
3
GYRO_YOUT_L[0]
4
GYRO_ZOUT_L[0]
5
ACCEL_XOUT_L[0]
6
ACCEL_YOUT_L[0]
7
ACCEL_ZOUT_L[0]
The DLPF is configured by DLPF_CFG. The accelerometer and gyroscope are filtered according to
the value of DLPF_CFG as shown in the table below.
DLPF_CFG
Accelerometer
(F
s
= 1kHz)
Gyroscope
Bandwidth
(Hz)
Delay
(ms)
Bandwidth
(Hz)
Delay
(ms)
Fs (kHz)
0
260
0
256
0.98
8
1
184
2.0
188
1.9
1
2
94
3.0
98
2.8
1
3
44
4.9
42
4.8
1
4
21
8.5
20
8.3
1
5
10
13.8
10
13.4
1
6
5
19.0
5
18.6
1
7
RESERVED
RESERVED
8
Bit 7 and bit 6 are reserved.
Parameters:
EXT_SYNC_SET 3-bit unsigned value. Configures the FSYNC pin sampling.
DLPF_CFG 3-bit unsigned value. Configures the DLPF setting.