User manual

49
Serial Bus Analysis
12.3 Parallel / Parallel Clocked BUS
The R&S®HMO Compact series has a PARALLEL and PA-
RALLEL CLOCKED BUS function installed ex factory and
is able to analyze up to 7 bit lines. The soft menu key BUS
WIDTH and the universal knob allow you to select the
number of bit lines. The soft menu keys PREV./NEXT BIT
allow you to move the position of the selection bar for the
source of the individual bits. The selected bit is highlighted
inblue.Theleftsideofthetablecontainsthebitsinxed
sequence, beginning at the top with D0 (= LSB). The uni-
versal knob allows you to assign a real logic channel to the
selected BUS bit. The allocation is not subject to restric-
tions; you can also use partially identical logic channels in
the two possible buses. If you select PARALLEL CLOCKED
as BUS TYPE, you can also use the bottom soft menu key
CONTROL WIRES to select sources for CHIP SELECT, and
you can use the universal knob to select the settings for
CLOCK. The soft menu key ACTIVE is used to determine if
the chip select signal High or Low Active is selected. The
soft menu key SLOPE allows you to toggle between rising,
falling and both slopes. The active selection is always high-
lighted in blue and is listed in the bit source window. Press
the MENU OFF button to return to the BUS main menu.
To trigger on parallel buses, it is recommended to use the
logic trigger (see chapter 6.5).
12.4 I
2
C BUS
The I
2
C BUS is a two-wire bus which was developed by
Philips (today known as NXP Semiconductor). A I
2
C BUS
has the following properties:
❙ Two wire bus (2-wire): Clock (SCL) and data (SDA)
❙ Master-Slave Communication: the master provides the
clock pulse and selects the slave
❙ Addressing: Each slave can be addressed via unique
address; multiple slaves can be linked with each other and
can be addressed by the same master
❙ Read/Write bit: Master reads data (=1) or writes data (=0)
❙ Acknowledge: issued after each byte
The format of a simple I
2
C message (frame) with an
address length of 7 bit is structured as follows:
❙ Start condition: Falling slope on SDA (Serial Data), while
SCL (Serial Clock) is HIGH
❙ 7 bit address (write or read slave)
❙ Read/Write bit (R/W): Indicates, if the data is to be
written or read out from the slave
❙ Acknowledge bit (ACK): Is issued by the recipient of the
previous byte if transmission was successful (exception:
for read access, the master terminates the data
transmission with a NACK bit after the last byte)
❙ Data: a series of data bytes with a ACK bit after each byte
❙ Stop condition: rising slope on SDA (Serial Data), while
SCL (Serial Clock) is HIGH
12.4.1 I
2
CBUSConguration
To decode the I
2
C BUS it is necessary to determine du-
ringthebuscongurationwhichlogicchannelwillbecon-
nected to the clock (SCL) and which one to the data line
(SDA). This setting is selected after choosing the BUS
TYPE I
2
C in the BUS menu and pressing the soft menu key
CONFIGURATION. In the menu, choose the top soft menu
key CLOCK SCL and use the universal knob in the CUR-
SOR/MENU section to select the source channel. You can
denethedatachannelbypressingthesoftmenukey
DATA SDA. A small window provides information about
the current settings. Press the MENU OFF button twice to
close all menus.
Certain portions of the I
2
C messages will be displayed in
color to distinguish between the different elements. If the
data lines are selected with the table display, the respec-
tive sections will also be displayed in color. These are de-
scribed as follows:
❙ Read address: Yellow
❙ Write address: Magenta
❙ Data: Cyan
❙ Start: White
❙ Stop: White
❙ No acknowledge: Red
❙ Acknowledge: Green
Prior to the BUS conguration it is necessary to set the correct
logic level (threshold). Please refer to chapter 4.5. The default
setting is 500 mV.
If the option R&S®HOO11 resp. the voucher R&S®HV111 is ins-
talled, it it only possible to select analog channels as source. If
the option R&S®HOO10 resp. the voucher R&S®HV110 is installed,
both analog and digital channels are available as source.
Fig.12.5:MenuforthedenitionofI
2
C sources
Fig. 12.4: I
2
C 7 bit address