Datasheet

BATTERY PROTECTION IC FOR SINGLE-CELL PACK
Rev.4.1_00
S-8261 Series
Seiko Instruments Inc.
7
 Pin Configurations
Table 5
Pin No. Symbol Description
1 DO
FET gate control pin for discharge
(CMOS output)
2 VM
Voltage detection pin between VM and VSS
(Overcurrent detection pin)
3 CO
FET gate control pin for charge
(CMOS output)
4 DP Test pin for delay time measurement
5 VDD Positive power input pin
6 VSS Negative power input pin
SOT-23-6
Top view
6
4 5
1 2 3
Figure 2
Table 6
Pin No. Symbol Description
1 CO
FET gate control pin for charge
(CMOS output)
2 VM
Voltage detection pin between VM and VSS
(Overcurrent detection pin)
3 DO
FET gate control pin for discharge
(CMOS output)
4 VSS Negative power input pin
5 DP Test pin for delay time measurement
6 VDD Positive power input pin
6-Pin SNB(B)
Top view
6 5 4
1 2 3
4 5 6
3 2 1
Bottom view
*1
*1. Connect the heatsink of back
side at shadowed area to the
board, and set electric
potential open or VDD.
However, do not use it
as
the function of electrode.
Figure 3