Specifications

CC1101
SWRS061I Page 32 of 98
clock pulses). The burst access is either a
read or a write access and must be terminated
by setting CSn high.
For register addresses in the range 0x30-
0x3D, the burst bit is used to select between
status registers when burst bit is one, and
between command strobes when burst bit is
zero. See more in Section 10.3 below.
Because of this, burst access is not available
for status registers and they must be accessed
one at a time. The status registers can only be
read.
10.3 SPI Read
When reading register fields over the SPI
interface while the register fields are updated
by the radio hardware (e.g. MARCSTATE or
TXBYTES), there is a small, but finite,
probability that a single read from the register
is being corrupt. As an example, the
probability of any single read from TXBYTES
being corrupt, assuming the maximum data
rate is used, is approximately 80 ppm. Refer to
the CC1101 Errata Notes [3] for more details.
10.4 Command Strobes
Command Strobes may be viewed as single
byte instructions to CC1101 . By addressing a
command strobe register, internal sequences
will be started. These commands are used to
disable the crystal oscillator, enable receive
mode, enable wake-on-radio etc. The 13
command strobes are listed in Table 42 on
page 67.
The command strobe registers are accessed
by transferring a single header byte (no data is
being transferred). That is, only the R/W¯ bit,
the burst access bit (set to 0), and the six
address bits (in the range 0x30 through 0x3D)
are written. The R/W¯ bit can be either one or
zero and will determine how the
FIFO_BYTES_AVAILABLE field in the status
byte should be interpreted.
When writing command strobes, the status
byte is sent on the SO pin.
A command strobe may be followed by any
other SPI access without pulling CSn high.
However, if an SRES strobe is being issued,
one will have to wait for SO to go low again
before the next header byte can be issued as
shown in Figure 16. The command strobes are
executed immediately, with the exception of
the SPWD, SWOR, and the SXOFF strobes,
which are executed when CSn goes high.
SI
Header
SRES
Header
Addr
Data
SO
CSn
Figure 16: SRES Command Strobe
10.5 FIFO Access
The 64-byte TX FIFO and the 64-byte RX
FIFO are accessed through the 0x3F address.
When the R/W¯ bit is zero, the TX FIFO is
accessed, and the RX FIFO is accessed when
the R/W¯ bit is one.
The TX FIFO is write-only, while the RX FIFO
is read-only.
The burst bit is used to determine if the FIFO
access is a single byte access or a burst
access. The single byte access method
Note: An SIDLE strobe will clear all
pending command strobes until IDLE
state is reached. This means that if for
example an SIDLE strobe is issued
while the radio is in RX state, any other
command strobes issued before the
radio reaches IDLE state will be
ignored.