Specifications

CC1101
SWRS061I Page 30 of 98
0
A5 A4 A3 A2 A0 A1
D
W
7
1
Read from register:
Write to register:
Hi-Z
X
SCLK:
CSn:
SI
SO
SI
SO
Hi-Z
t
sp
t
ch
t
cl
t
sd
t
hd
t
ns
X
X
Hi-Z
X
Hi-Z
S7
X
D
W
6 D
W
5 D
W
4 D
W
3 D
W
2 D
W
1 D
W
0
B
S5
S4
S3 S2 S1 S0
S7
S6
S5 S4 S3
S2
S1 S0
B
B
A5 A4 A3 A2 A1 A0
S7
B S5 S4 S3 S2 S1 S0
D
R
7 D
R
6 D
R
5 D
R
4 D
R
3 D
R
2 D
R
1 D
R
0
Figure 15: Configuration Registers Write and Read Operations
Parameter
Description
Min
Max
Units
f
SCLK
SCLK frequency
100 ns delay inserted between address byte and data byte (single access), or
between address and data, and between each data byte (burst access).
-
10
MHz
SCLK frequency, single access
No delay between address and data byte
-
9
SCLK frequency, burst access
No delay between address and data byte, or between data bytes
-
6.5
t
sp,pd
CSn low to positive edge on SCLK, in power-down mode
150
-
s
t
sp
CSn low to positive edge on SCLK, in active mode
20
-
ns
t
ch
Clock high
50
-
ns
t
cl
Clock low
50
-
ns
t
rise
Clock rise time
-
40
ns
t
fall
Clock fall time
-
40
ns
t
sd
Setup data (negative SCLK edge) to
positive edge on SCLK
(t
sd
applies between address and data bytes, and between
data bytes)
Single access
Burst access
55
76
-
-
ns
t
hd
Hold data after positive edge on SCLK
20
-
ns
t
ns
Negative edge on SCLK to CSn high.
20
-
ns
Table 22: SPI Interface Timing Requirements
Note: The minimum t
sp,pd
figure in Table 22 can be used in cases where the user does not read
the CHIP_RDYn signal. CSn low to positive edge on SCLK when the chip is woken from power-
down depends on the start-up time of the crystal being used. The 150 μs in Table 22 is the
crystal oscillator start-up time measured on CC1101EM reference designs ([1] and [2]) using
crystal AT-41CD2 from NDK.