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CC1101

SWRS061I Page 1 of 98

Low-Power Sub-1 GHz RF Transceiver

Applications

 Ultra low-power wireless applications

operating in the 315/433/868/915 MHz

ISM/SRD bands

 Wireless alarm and security systems

 Industrial monitoring and control

 Wireless sensor networks

 AMR – Automatic Meter Reading

 Home and building automation

 Wireless MBUS

Product Description

CC1101

is a low-cost sub-1 GHz transceiver

designed for very low-power wireless appli-

cations. The circuit is mainly intended for the

ISM (Industrial, Scientific and Medical) and

SRD (Short Range Device) frequency bands

at 315, 433, 868, and 915 MHz, but can easily

be programmed for operation at other

frequencies in the 300-348 MHz, 387-464 MHz

and 779-928 MHz bands.

The RF transceiver is integrated with a highly

configurable baseband modem. The modem

supports various modulation formats and has

a configurable data rate up to 600 kbps.

CC1101

provides extensive hardware support

for packet handling, data buffering, burst

transmissions, clear channel assessment, link

quality indication, and wake-on-radio.

The main operating parameters and the 64-

byte transmit/receive FIFOs of

CC1101

can be

controlled via an SPI interface. In a typical

system, the

CC1101

will be used together with a

microcontroller and a few additional passive

components.

The

CC1190

850-950 MHz range extender [21]

can be used with

CC1101

in long range

applications for improved sensitivity and higher

output power.

CC1101

Summary of content (105 pages)

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CC1101 Low-Power Sub-1 GHz RF Transceiver Applications  Ultra low-power wireless applications operating in the 315/433/868/915 MHz ISM/SRD bands  Wireless alarm and security systems  Industrial monitoring and control     Wireless sensor networks AMR – Automatic Meter Reading Home and building automation Wireless MBUS Product Description 16 17 The CC1190 850-950 MHz range extender [21] can be used with CC1101 in long range applications for improved sensitivity and higher output power.
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CC1101 Key Features RF Performance Low-Power Features         High sensitivity o -116 dBm at 0.6 kBaud, 433 MHz, 1% packet error rate o -112 dBm at 1.2 kBaud, 868 MHz, 1% packet error rate Low current consumption (14.7 mA in RX, 1.2 kBaud, 868 MHz) Programmable output power up to +12 dBm for all supported frequencies Excellent receiver selectivity and blocking performance Programmable data rate from 0.
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CC1101 Reduced Battery Current using TPS62730    The TPS62730 [26] is a step down converter with bypass mode for ultra low power wireless applications. In RX, the current drawn from a 3.6 V battery is typically less than 11 mA when TPS62730 output voltage is 2.1 V. When connecting CC1101 directly to a 3.6 V battery the current drawn is typically 17 mA (see Figure 1) In TX, at maximum output power (+12 dBm), the current drawn from a 3.
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CC1101 Abbreviations Abbreviations used in this data sheet are described below.
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CC1101 Table Of Contents APPLICATIONS .................................................................................................................................................. 1 PRODUCT DESCRIPTION ................................................................................................................................ 1 KEY FEATURES .................................................................................................................................................
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CC1101 13 14 14.1 14.2 14.3 15 15.1 15.2 15.3 15.4 15.5 15.6 16 16.1 16.2 16.3 17 17.1 17.2 17.3 17.4 17.5 17.6 18 18.1 18.2 19 19.1 19.2 19.3 19.4 19.5 19.6 19.7 20 21 22 22.1 23 24 25 26 27 27.1 27.2 28 28.1 28.2 28.3 28.4 28.5 28.6 28.7 28.8 RECEIVER CHANNEL FILTER BANDWIDTH .............................................................................. 35 DEMODULATOR, SYMBOL SYNCHRONIZER, AND DATA DECISION .................................. 36 FREQUENCY OFFSET COMPENSATION...............................
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CC1101 29 29.1 29.2 29.3 30 31 32 33 33.1 CONFIGURATION REGISTERS ........................................................................................................ 66 CONFIGURATION REGISTER DETAILS – REGISTERS WITH PRESERVED VALUES IN SLEEP STATE ............... 71 CONFIGURATION REGISTER DETAILS – REGISTERS THAT LOOSE PROGRAMMING IN SLEEP STATE ......... 91 STATUS REGISTER DETAILS.......................................................................................................................
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CC1101 1 Absolute Maximum Ratings Under no circumstances must the absolute maximum ratings given in Table 1 be violated. Stress exceeding one or more of the limiting values may cause permanent damage to the device. Parameter Min Max Units Supply voltage –0.3 3.9 V Voltage on any digital pin –0.3 VDD + 0.3, max 3.9 V Voltage on the pins RF_P, RF_N, DCOUPL, RBIAS –0.3 2.
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CC1101 4 Electrical Specifications 4.1 Current Consumption TA = 25C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the CC1101EM reference designs ([1] and [2]). Reduced current settings (MDMCFG2.DEM_DCFILT_OFF=1) gives a slightly lower current consumption at the cost of a reduction in sensitivity. See Table 7 for additional details on current consumption and sensitivity.
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CC1101 Parameter Current consumption, 433 MHz Current consumption, 868/915 MHz Min Typ Max Unit Condition 16.0 mA Receive mode, 1.2 kBaud, register settings optimized for reduced current, input at sensitivity limit 15.0 mA Receive mode, 1.2 kBaud, register settings optimized for reduced current, input well above sensitivity limit 15.7 mA Receive mode, 38.4 kBaud, register settings optimized for reduced current, input at sensitivity limit 15.0 mA Receive mode, 38.
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CC1101 Temperature [°C] Current [mA], PATABLE=0xC0, +12 dBm Current [mA], PATABLE=0xC5, +10 dBm Current [mA], PATABLE=0x50, 0 dBm Supply Voltage VDD = 1.8 V -40 25 85 Supply Voltage VDD = 3.0 V -40 25 85 Supply Voltage VDD = 3.6 V -40 25 85 32.7 31.5 30.5 35.3 34.2 33.3 35.5 34.4 33.5 30.1 29.2 28.3 30.9 30.0 29.4 31.1 30.3 29.6 16.4 16.0 15.6 17.3 16.8 16.4 17.6 17.1 16.
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CC1101 4.2 RF Receive Section TA = 25C, VDD = 3.0 V if nothing else stated. All measurement results are obtained using the CC1101EM reference designs ([1] and [2]). Parameter Min Digital channel filter bandwidth 58 Spurious emissions Typ Max Unit Condition/Note 812 kHz User programmable. The bandwidth limits are proportional to crystal frequency (given values assume a 26.
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CC1101 Parameter Blocking ±2 MHz offset ±10 MHz offset Min Typ -50 -40 Max Unit Condition/Note dBm dBm Desired channel 3 dB above the sensitivity limit See Figure 4 for blocking performance at other offset frequencies 38.4 kBaud data rate, sensitivity optimized, MDMCFG2.DEM_DCFILT_OFF=0 (GFSK, 1% packet error rate, 20 bytes packet length, 20 kHz deviation, 100 kHz digital channel filter bandwidth) Receiver sensitivity –104 dBm Sensitivity can be traded for current consumption by setting MDMCFG2.
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CC1101 Temperature [°C] Sensitivity [dBm] 1.2 kBaud Sensitivity [dBm] 38.4 kBaud Sensitivity [dBm] 250 kBaud Sensitivity [dBm] 500 kBaud Supply Voltage VDD = 1.8 V -40 25 85 Supply Voltage VDD = 3.0 V -40 25 85 Supply Voltage VDD = 3.
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CC1101 70 50 60 40 50 30 Selectivity [dB] Blocking [dB] 40 30 20 20 10 10 0 -1 0 -40 -30 -20 -10 0 10 20 30 -0,9 -0,8 -0,7 -0,6 -0,5 -0,4 -0,3 -0,2 -0,1 0 0,1 0,2 0,3 0,4 0,5 0,6 0,7 0,8 0,9 1 40 -10 -10 -20 -20 Offset [MHz] Offset [MHz] Figure 5: Typical Selectivity at 38.4 kBaud Data Rate, 868 MHz, GFSK, 20 kHz Deviation. IF Frequency is 152.
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CC1101 4.3 RF Transmit Section TA = 25C, VDD = 3.0 V, +10 dBm if nothing else stated. All measurement results are obtained using the CC1101EM reference designs ([1] and [2]). Parameter Min Typ Max Unit Differential load impedance 122 + j31  433 MHz 116 + j41  868/915 MHz 86.
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CC1101 Parameter Min Typ Max Unit Condition/Note Spurious emissions conducted, harmonics not included 315 MHz < -58 < -53 dBm dBm Measured with +10 dBm CW at 315 MHz and 433 MHz Frequencies below 960 MHz Frequencies above 960 MHz 433 MHz < -50 < -54 < -56 dBm dBm dBm Frequencies below 1 GHz Frequencies above 1 GHz Frequencies within 47-74, 87.
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CC1101 4.4 Crystal Oscillator TA = 25C, VDD = 3.0 V if nothing else is stated. All measurement results obtained using the CC1101EM reference designs ([1] and [2]). Parameter Crystal frequency Min Typ Max Unit Condition/Note 26 26 27 MHz For compliance with modulation bandwidth requirements under EN 300 220 in the 863 to 870 MHz frequency range it is recommended to use a 26 MHz crystal for frequencies below 869 MHz and a 27 MHz crystal for frequencies above 869 MHz.
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CC1101 4.6 Frequency Synthesizer Characteristics TA = 25C, VDD = 3.0 V if nothing else is stated. All measurement results are obtained using the CC1101EM reference designs ([1] and [2]). Min figures are given using a 27 MHz crystal. Typ and max figures are given using a 26 MHz crystal. Parameter Programmed frequency resolution Min Typ 397 Max FXOSC/ 216 Unit 412 Condition/Note Hz 26-27 MHz crystal. The resolution (in Hz) is equal for all frequency bands Given by crystal used.
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CC1101 4.8 DC Characteristics TA = 25C if nothing else stated. Digital Inputs/Outputs Min Max Unit Logic "0" input voltage 0 0.7 V Logic "1" input voltage Condition VDD-0.7 VDD V Logic "0" output voltage 0 0.5 V For up to 4 mA output current Logic "1" output voltage VDD-0.3 VDD V For up to 4 mA output current Logic "0" input current N/A –50 nA Input equals 0V Logic "1" input current N/A 50 nA Input equals VDD Table 17: DC Characteristics 4.
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CC1101 Pin # Pin Name Pin type Description 1 SCLK Digital Input Serial configuration interface, clock input 2 SO (GDO1) Digital Output Serial configuration interface, data output Optional general output pin when CSn is high 3 GDO2 Digital Output Digital output pin for general use:  Test signals  FIFO status signals  Clear channel indicator  Clock output, down-divided from XOSC  Serial output RX data 4 DVDD Power (Digital) 1.8 - 3.
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CC1101 6 Circuit Description 90 PA RC OSC BIAS RBIAS XOSC XOSC_Q1 RXFIFO DIGITAL INTERFACE TO MCU FREQ SYNTH 0 RF_N MODULATOR RF_P TXFIFO ADC PACKET HANDLER LNA FEC / INTERLEAVER ADC DEMODULATOR RADIO CONTROL SCLK SO (GDO1) SI CSn GDO0 (ATEST) GDO2 XOSC_Q2 Figure 9: CC1101 Simplified Block Diagram A simplified block diagram of CC1101 is shown in Figure 9. CC1101 features a low-IF receiver.
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CC1101 7.2 Balun and RF Matching The balanced RF input and output of CC1101 share two common pins and are designed for a simple, low-cost matching and balun network on the printed circuit board. The receive- and transmit switching at the CC1101 front-end is controlled by a dedicated on-chip function, eliminating the need for an external RX/TXswitch. DC blocking. Together with an appropriate LC network, the balun components also transform the impedance to match a 50  load.
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CC1101 and C101 can be omitted when using a 7.5 Additional Filtering In the 868/915 MHz reference design, C126 and L125 together with C125 build an optional filter to reduce emission at carrier frequency – 169 MHz. This filter is necessary for applications with an external antenna connector that seek compliance with ETSI EN 300-220. For more information, see DN017 [9]. 7.6 If this filtering is not necessary, C125 will work as a DC block (only necessary if there is a DC path in the antenna).
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CC1101 1.8V-3.6V power supply R171 2 SO (GDO1) 3 GDO2 GND 16 RBIAS 17 DGUARD 18 SI 20 1 SCLK SO (GDO1) GDO2 (optional) CC1101 AVDD 14 C131 L131 C125 RF_N 13 DIE ATTACH PAD: 9 AVDD 8 XOSC_Q1 7 CSn 6 GDO0 10 XOSC_Q2 RF_P 12 5 DCOUPL C51 Antenna (50 Ohm) AVDD 15 4 DVDD AVDD 11 C121 L122 L121 L123 C122 C123 C124 GDO0 (optional) CSn XTAL C81 C101 Figure 10: Typical Application and Evaluation Circuit 315/433 MHz (excluding supply decoupling capacitors) 1.8V-3.
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CC1101 Component Value at 315MHz Value at 433MHz Value at 868/915MHz Manufacturer C51 100 nF ± 10%, 0402 X5R Murata GRM1555C series C81 27 pF ± 5%, 0402 NP0 Murata GRM1555C series C101 27 pF ± 5%, 0402 NP0 Murata GRM1555C series C121 6.8 pF ± 0.5 pF, 0402 NP0 3.9 pF ± 0.25 pF, 0402 NP0 1.0 pF ± 0.25 pF, 0402 NP0 Murata GRM1555C series C122 12 pF ± 5%, 0402 NP0 8.2 pF ± 0.5 pF, 0402 NP0 1.5 pF ± 0.25 pF, 0402 NP0 Murata GRM1555C series C123 6.8 pF ± 0.5 pF, 0402 NP0 5.6 pF ± 0.
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CC1101 reflow process, which may cause defects (splattering, solder balling). Using “tented” vias reduces the solder paste coverage below 100%. See Figure 12 for top solder resist and top paste masks. Each decoupling capacitor should be placed as close as possible to the supply pin it is supposed to decouple. Each decoupling capacitor should be connected to the power line (or power plane) by separate vias.
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CC1101 CC1101 state machine, and a complete state diagram, see Section 19, starting on page 50. Sleep SPWD or wake-on-radio (WOR) SIDLE Default state when the radio is not receiving or transmitting. Typ. current consumption: 1.7 mA. CSn = 0 Lowest power mode. Most register values are retained. Current consumption typ 200 nA, or typ 500 nA when wake-on-radio (WOR) is enabled. IDLE SXOFF Used for calibrating frequency synthesizer upfront (entering receive or transmit mode can Manual freq.
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CC1101 9 Configuration Software CC1101 can be configured using the SmartRFTM After chip reset, all the registers have default values as shown in the tables in Section 29. The optimum register setting might differ from the default value. After a reset all registers that shall be different from the default value therefore needs to be programmed through the SPI interface. Studio software [5].
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CC1101 tsp tch tcl tsd thd tns SCLK: CSn: Write to register: SI X 0 B A5 SO Hi-Z S7 B S5 SI X A4 A3 A2 A1 A0 S4 S3 S2 S1 S0 X DW7 DW6 S6 S7 DW5 S5 DW4 DW3 DW2 DW1 DW0 S3 S2 S1 S0 DR2 DR1 S4 X Hi-Z Read from register: SO Hi-Z 1 B A5 A4 A3 A2 A1 A0 S7 B S5 S4 S3 S2 S1 S0 X DR7 DR6 DR5 DR4 DR3 DR0 Hi-Z Figure 15: Configuration Registers Write and Read Operations Parameter Description Min Max Units fSCLK SCLK frequency - 10 MHz -
PAGE 31
CC1101 10.1 Chip Status Byte When the header byte, data byte, or command strobe is sent on the SPI interface, the chip status byte is sent by the CC1101 on the SO pin. The status byte contains key status signals, useful for the MCU. The first bit, s7, is the CHIP_RDYn signal and this signal must go low before the first positive edge of SCLK. The CHIP_RDYn signal indicates that the crystal is running. Bits 6, 5, and 4 comprise the STATE value. This value reflects the state of the chip.
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CC1101 clock pulses). The burst access is either a read or a write access and must be terminated by setting CSn high. For register addresses in the range 0x300x3D, the burst bit is used to select between status registers when burst bit is one, and between command strobes when burst bit is zero. See more in Section 10.3 below. Because of this, burst access is not available for status registers and they must be accessed one at a time. The status registers can only be read. 10.
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CC1101 expects a header byte with the burst bit set to zero and one data byte. After the data byte, a new header byte is expected; hence, CSn can remain low. The burst access method expects one header byte and then consecutive data bytes until terminating the access by setting CSn high. underflow while writing data to the TX FIFO. Note that the status byte contains the number of bytes free before writing the byte in progress to the TX FIFO.
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CC1101 11 Microcontroller Interface and Pin Configuration In a typical system, CC1101 will interface to a microcontroller. This microcontroller must be able to:  Program CC1101 into different modes  Read and write buffered data  Read back status information via the 4-wire SPI-bus configuration interface (SI, SO, SCLK and CSn) 11.1 Configuration Interface The microcontroller uses four I/O pins for the SPI configuration interface (SI, SO, SCLK and CSn). The SPI is described in Section 10 on page 29.
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CC1101 12 Data Rate Programming The data rate used when transmitting, or the data rate expected in receive is programmed by the MDMCFG3.DRATE_M and the MDMCFG4.DRATE_E configuration registers. The data rate is given by the formula below. As the formula shows, the programmed data rate depends on the crystal frequency.
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CC1101 14 Demodulator, Symbol Synchronizer, and Data Decision CC1101 contains an advanced and highly configurable demodulator. Channel filtering and frequency offset compensation is performed digitally. To generate the RSSI level (see Section 17.3 for more information), the signal level in the channel is estimated. Data filtering is also included for enhanced performance. 14.1 Frequency Offset Compensation The CC1101 has a very fine frequency resolution (see Table 15).
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CC1101 15 Packet Handling Hardware Support The CC1101 has built-in hardware support for packet oriented radio protocols. In transmit mode, the packet handler can be configured to add the following elements to the packet stored in the TX FIFO:    A programmable number of preamble bytes A two byte synchronization (sync) word. Can be duplicated to give a 4-byte sync word (recommended). It is not possible to only insert preamble or only insert a sync word A CRC checksum computed over the data field.
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CC1101 8 TX_DATA 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 The first TX_DATA byte is shifted in before doing the XOR-operation providing the first TX_OUT[7:0] byte. The second TX_DATA byte is then shifted in before doing the XOR-operation providing the second TX_OUT[7:0] byte. TX_OUT[7:0] Figure 18: Data Whitening in TX Mode 15.
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CC1101 packets, infinite packet length mode must be used. Fixed packet length mode is selected by setting PKTCTRL0.LENGTH_CONFIG=0. The desired packet length is set by the PKTLEN register. This value must be different from 0. In variable packet length mode, PKTCTRL0.LENGTH_CONFIG=1, the packet length is configured by the first byte after the sync word. The packet length is defined as the payload data, excluding the length byte and the optional CRC.
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CC1101 Internal byte counter in packet handler counts from 0 to 255 and then starts at 0 again 0,1,..........,88,....................255,0,........,88,..................,255,0,........,88,..................,255,0,....................... Infinite packet length enabled Fixed packet length enabled when less than 256 bytes remains of packet 600 bytes transmitted and received Length field transmitted and received. Rx and Tx PKTLEN value set to mod(600,256) = 88 Figure 20: Packet Length > 255 15.
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CC1101 The modulator will first send the programmed number of preamble bytes. If data is available in the TX FIFO, the modulator will send the two-byte (optionally 4-byte) sync word followed by the payload in the TX FIFO. If CRC is enabled, the checksum is calculated over all the data pulled from the TX FIFO, and the result is sent as two extra bytes following the payload data. If the TX FIFO runs empty before the complete packet has been transmitted, the radio will enter TXFIFO_UNDERFLOW state.
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CC1101 MISO line each time a header byte, data byte, or command strobe is sent on the SPI bus. is a small, but finite, probability that a single read from registers PKTSTATUS , RXBYTES and TXBYTES is being corrupt. The same is the case when reading the chip status byte. It is recommended to employ an interrupt driven solution since high rate SPI polling reduces the RX sensitivity. Furthermore, as explained in Section 10.
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CC1101 16.2 Minimum Shift Keying 2 When using MSK , the complete transmission (preamble, sync word, and payload) will be MSK modulated. This is equivalent to changing the shaping of the symbol. The DEVIATN register setting has no effect in RX when using MSK. Phase shifts are performed with a constant transition time. The fraction of a symbol period used to change the phase can be modified with the DEVIATN.DEVIATION_M setting.
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CC1101 MDMCFG2.SYNC_MODE Sync Word Qualifier Mode 000 No preamble/sync 001 15/16 sync word bits detected 010 16/16 sync word bits detected 011 30/32 sync word bits detected 100 No preamble/sync + carrier sense above threshold 101 15/16 + carrier sense above threshold 110 16/16 + carrier sense above threshold 111 30/32 + carrier sense above threshold Table 30: Sync Word Qualifier Mode 17.
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CC1101 4) Else if RSSI_dec < 128 then RSSI_dBm = (RSSI_dec)/2 – RSSI_offset typical plots of RSSI readings as a function of input power level for different data rates. Table 31 gives typical values for the RSSI_offset. Figure 22 and Figure 23 show Data rate [kBaud] RSSI_offset [dB], 433 MHz RSSI_offset [dB], 868 MHz 1.2 74 74 38.
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CC1101 0 -10 -20 RSSI Readout [dBm] -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -120 -110 -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 Input Power [dBm] 1.2 kBaud 250 kBaud 38.4 kBaud 500 kBaud Figure 23: Typical RSSI Value vs. Input Power Level for Different Data Rates at 868 MHz 17.4 Carrier Sense (CS) Carrier sense (CS) is used as a sync word qualifier and for Clear Channel Assessment (see Section 17.5).
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CC1101 If the threshold is set high, i.e. only strong signals are wanted, the threshold should be adjusted upwards by first reducing the MAX_LNA_GAIN value and then the MAX_DVGA_GAIN value. This will reduce power consumption in the receiver front end, since the highest gain settings are avoided. MAX_DVGA_GAIN[1:0] MAX_LNA_GAIN[2:0] 33 show the typical RSSI readout values at the CS threshold at 2.4 kBaud and 250 kBaud data rate respectively.
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CC1101 17.5 Clear Channel Assessment (CCA) The Clear Channel Assessment (CCA) is used to indicate if the current channel is free or busy. The current CCA state is viewable on any of the GDO pins by setting IOCFGx.GDOx_CFG=0x09. becomes available, the radio will not enter TX or FSTXON state before a new strobe command is sent on the SPI interface. This feature is called TX-if-CCA. Four CCA requirements can be programmed: MCSM1.CCA_MODE selects the mode to use when determining CCA.
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CC1101 18.2 Interleaving Data received through radio channels will often experience burst errors due to interference and time-varying signal strengths. In order to increase the robustness to errors spanning multiple bits, interleaving is used when FEC is enabled. After de-interleaving, a continuous span of errors in the received stream will become single errors spread apart. passed onto the convolutional decoder is read from the columns of the matrix.
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CC1101 19 Radio Control SIDLE SPWD | SWOR SLEEP 0 CAL_COMPLETE MANCAL 3,4,5 IDLE 1 CSn = 0 | WOR SXOFF SCAL CSn = 0 XOFF 2 SRX | STX | SFSTXON | WOR FS_WAKEUP 6,7 FS_AUTOCAL = 01 & SRX | STX | SFSTXON | WOR FS_AUTOCAL = 00 | 10 | 11 & SRX | STX | SFSTXON | WOR SETTLING 9,10,11 SFSTXON CALIBRATE 8 CAL_COMPLETE FSTXON 18 STX SRX STX TXOFF_MODE=01 SFSTXON | RXOFF_MODE = 01 STX | RXOFF_MODE = 10 TXOFF_MODE = 10 SRX | WOR RXTX_SETTLING 21 TX 19,20 SRX | TXOFF_MODE = 11 TXOFF_MODE = 00 & F
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CC1101 change the signal that is output on the GDO0 pin. The default setting is to output a clock signal with a frequency of CLK_XOSC/192. However, to optimize performance in TX and RX, an alternative GDO setting from the settings found in Table 41 on page 62 should be selected. this strobe, all internal registers and states are set to the default, IDLE state.
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CC1101 19.3 Voltage Regulator Control The voltage regulator to the digital core is controlled by the radio controller. When the chip enters the SLEEP state which is the state with the lowest current consumption, the voltage regulator is disabled. This occurs after CSn is released when a SPWD command strobe has been sent on the SPI interface. The chip is then in the SLEEP state. Setting CSn low again will turn on the regulator and crystal oscillator and make the chip enter the IDLE state.
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CC1101 19.5 Wake On Radio (WOR) The optional Wake on Radio (WOR) functionality enables CC1101 to periodically wake up from SLEEP and listen for incoming packets without MCU interaction. When the SWOR strobe command is sent on the SPI interface, the CC1101 will go to the SLEEP state when CSn is released. The RC oscillator must be enabled before the SWOR strobe can be used, as it is the clock source for the WOR timer. The on-chip timer will set CC1101 into IDLE state and then RX state.
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CC1101 RCCTRL0 and RCCTRL1 respectively. If the RC oscillator calibration is turned off, it will have to be manually turned on again if temperature and supply voltage changes. Refer to Application Note AN047 [4] for further details. 19.6 Timing 19.6.1 Overall State Transition Times The main radio controller needs to wait in certain states in order to make sure that the internal analog/digital parts have settled down and are ready to operate in the new states.
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CC1101 TEST0 FSCAL3.CHP_CURR_CAL_EN 0x09 00b 3764/fxosc = 145 us 3764/fxosc = 139 us 0x09 10b 18506/fxosc = 712 us 18506/fxosc = 685 us 0x0B 00b 4073/fxosc = 157 us 4073/fxosc = 151 us 0x0B 10b 18815/fxosc = 724 us 18815/fxosc = 697 us FS Calibration Time fxosc = 26 MHz FS Calibration Time fxosc = 27 MHz Table 35: Frequency Synthesizer Calibration Times (26/27 MHz crystal) 19.7 RX Termination Timer CC1101 has optional functions for automatic termination of RX after a programmable time.
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CC1101 20 Data FIFO The CC1101 contains two 64 byte FIFOs, one for received data and one for data to be transmitted. The SPI interface is used to read from the RX FIFO and write to the TX FIFO. Section 10.5 contains details on the SPI FIFO access. The FIFO controller will detect overflow in the RX FIFO and underflow in the TX FIFO. When writing to the TX FIFO it is the responsibility of the MCU to avoid TX FIFO overflow. A TX FIFO overflow will result in an error in the TX FIFO content.
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CC1101 NUM_RXBYTES Overflow margin 53 54 55 56 57 56 55 54 53 GDO FIFO_THR=13 NUM_TXBYTES 6 7 8 9 10 9 8 7 6 GDO Figure 30: Number of Bytes in FIFO vs. the GDO Signal (GDOx_CFG=0x00 in RX and GDOx_CFG=0x02 in TX, FIFO_THR=13) 56 bytes FIFO_THR=13 Underflow margin 8 bytes RXFIFO TXFIFO Figure 29: Example of FIFOs at Threshold 21 Frequency Programming The frequency programming in CC1101 is designed to minimize the programming needed in a channel-oriented system.
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CC1101 22 VCO The VCO is completely integrated on-chip. 22.1 VCO and PLL Self-Calibration The VCO characteristics vary with temperature and supply voltage changes as well as the desired operating frequency. In order to ensure reliable operation, CC1101 includes frequency synthesizer self-calibration circuitry. This calibration should be done regularly, and must be performed after turning on power and before using a new frequency (or channel).
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CC1101 24 Output Power Programming The RF output power level from the device has two levels of programmability as illustrated in Figure 31. The special PATABLE register can hold up to eight user selected output power settings. The 3-bit FREND0.PA_POWER value selects the PATABLE entry to use. This twolevel functionality provides flexible PA power ramp up and ramp down at the start and end of transmission when using 2-FSK, GFSK, 4-FSK, and MSK modulation as well as ASK modulation shaping.
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CC1101 868 MHz 915 MHz Default Power Setting Output Power [dBm] Current Consumption, Typ. [mA] Output Power [dBm] 0xC6 9.6 29.4 8.9 Current Consumption, Typ. [mA] 28.7 Table 38: Output Power and Current Consumption for Default PATABLE Setting Using WireWound Inductors in 868/915 MHz Frequency Bands 315 MHz Output Power [dBm] Setting Current Consumption, Typ. [mA] -30 0x12 -20 433 MHz Setting Current Consumption, Typ. [mA] 10.9 0x12 0x0D 11.
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CC1101 PATABLE(7)[7:0] The PA uses this setting. PATABLE(6)[7:0] PATABLE(5)[7:0] PATABLE(4)[7:0] Settings 0 to PA_POWER are used during ramp-up at start of transmission and ramp-down at end of transmission, and for ASK/OOK modulation. PATABLE(3)[7:0] PATABLE(2)[7:0] PATABLE(1)[7:0] PATABLE(0)[7:0] Index into PATABLE(7:0) The SmartRF® Studio software should be used to obtain optimum PATABLE settings for various output powers. e.
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CC1101 GDOx_CFG[5:0] Description Associated to the RX FIFO: Asserts when RX FIFO is filled at or above the RX FIFO threshold. De-asserts when RX FIFO 0 (0x00) is drained below the same threshold. Associated to the RX FIFO: Asserts when RX FIFO is filled at or above the RX FIFO threshold or the end of packet is 1 (0x01) reached. De-asserts when the RX FIFO is empty. Associated to the TX FIFO: Asserts when the TX FIFO is filled at or above the TX FIFO threshold.
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CC1101 27 Asynchronous and Synchronous Serial Operation Several features and modes of operation have been included in the CC1101 to provide backward compatibility with previous Chipcon products and other existing RF communication systems. For new systems, it is recommended to use the built-in packet handling features, as they can give more robust communication, significantly offload the microcontroller, and simplify software development. 27.
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CC1101 RX_SYMBOL_TICK and RX_HARD_DATA, see Table 41. RX_HARD_DATA[1:0] is the hard decision symbol. RX_HARD_DATA[1:0] contain data for 4-ary modulation formats while RX_HARD_DATA[1] contain data for 2ary modulation formats. The RX_SYMBOL_TICK signal is the symbol clock and is high for one half symbol period whenever a new symbol is presented on the hard and soft data outputs. This option may be used for both synchronous and asynchronous interfaces. 28 System Considerations and Guidelines 28.
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CC1101 time is reduced from 712/724 µs to 145/157 µs (26 MHz crystal and TEST0 = 0x09/0B, see Table 35). The blanking interval between each frequency hop is then 220/232 µs. There is a trade off between blanking time and memory space needed for storing calibration data in non-volatile memory. Solution 2) above gives the shortest blanking interval, but requires more memory space to store calibration values.
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CC1101 often prevents this kind of continuous data streaming and reduces the effective data rate). 28.7 Battery Operated Systems In low power applications, the SLEEP state with the crystal oscillator core switched off should be used when the CC1101 is not active. It is possible to leave the crystal oscillator core running in the SLEEP state if start-up time is critical. The WOR functionality should be used in low power applications. 28.
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CC1101 Table 45 summarizes the SPI address space. The address to use is given by adding the base address to the left and the burst and read/write bits on the top. Note that the burst bit has different meaning for base addresses above and below 0x2F. Address Strobe Name Description 0x30 SRES Reset chip. 0x31 SFSTXON 0x32 SXOFF 0x33 SCAL Calibrate frequency synthesizer and turn it off. SCAL can be strobed from IDLE mode without setting manual calibration mode (MCSM0.
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CC1101 Preserved in SLEEP State Details on Page Number Yes 71 Yes 71 IOCFG0 GDO2 output pin configuration GDO1 output pin configuration GDO0 output pin configuration Yes 71 0x03 FIFOTHR RX FIFO and TX FIFO thresholds Yes 72 0x04 SYNC1 Sync word, high byte Yes 73 0x05 SYNC0 Sync word, low byte Yes 73 0x06 PKTLEN Packet length Yes 73 0x07 PKTCTRL1 Packet automation control Yes 73 0x08 PKTCTRL0 Packet automation control Yes 74 Address Register Description 0x00 IOCFG2
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CC1101 Address Register Description Details on page number 0x30 (0xF0) PARTNUM Part number for CC1101 92 0x31 (0xF1) VERSION Current version number 92 0x32 (0xF2) FREQEST Frequency Offset Estimate 92 0x33 (0xF3) LQI Demodulator estimate for Link Quality 92 0x34 (0xF4) RSSI Received signal strength indication 92 0x35 (0xF5) MARCSTATE Control state machine state 93 0x36 (0xF6) WORTIME1 High byte of WOR timer 93 0x37 (0xF7) WORTIME0 Low byte of WOR timer 93 0x38 (0xF8) PKTS
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CC1101 SRES SFSTXON SXOFF SCAL SRX STX SIDLE SRES SFSTXON SXOFF SCAL SRX STX SIDLE SWOR SPWD SFRX SFTX SWORRST SNOP PATABLE TX FIFO SWOR SPWD SFRX SFTX SWORRST SNOP PATABLE RX FIFO PATABLE TX FIFO SWRS061I Burst +0xC0 R/W configuration registers, burst access possible 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 0x15 0x16 0x17 0x18 0x19 0x1A 0x1B 0x1C 0x1D 0x1E 0x1F 0x20 0x21 0x22 0x23 0x24 0x25 0x26 0x27 0x28 0x29 0x2A 0x2B 0x2C 0x2D 0x2E
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CC1101 29.1 Configuration Register Details – Registers with preserved values in SLEEP state 0x00: IOCFG2 – GDO2 Output Pin Configuration Bit Field Name Reset 7 R/W Description R0 Not used 6 GDO2_INV 0 R/W Invert output, i.e. select active low (1) / high (0) 5:0 GDO2_CFG[5:0] 41 (0x29) R/W Default is CHP_RDYn (See Table 41 on page 62).
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CC1101 0x03: FIFOTHR – RX FIFO and TX FIFO Thresholds Bit Field Name 7 6 ADC_RETENTION Reset R/W Description 0 R/W Reserved , write 0 for compatibility with possible future extensions 0 R/W 0: TEST1 = 0x31 and TEST2= 0x88 when waking up from SLEEP 1: TEST1 = 0x35 and TEST2 = 0x81 when waking up from SLEEP Note that the changes in the TEST registers due to the ADC_RETENTION bit setting are only seen INTERNALLY in the analog part.
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CC1101 0x04: SYNC1 – Sync Word, High Byte Bit Field Name Reset R/W Description 7:0 SYNC[15:8] 211 (0xD3) R/W 8 MSB of 16-bit sync word 0x05: SYNC0 – Sync Word, Low Byte Bit Field Name Reset R/W Description 7:0 SYNC[7:0] 145 (0x91) R/W 8 LSB of 16-bit sync word 0x06: PKTLEN – Packet Length Bit Field Name Reset R/W Description 7:0 PACKET_LENGTH 255 (0xFF) R/W Indicates the packet length when fixed packet length mode is enabled.
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CC1101 0x08: PKTCTRL0 – Packet Automation Control Bit Field Name Reset 7 6 WHITE_DATA 1 R/W Description R0 Not used R/W Turn data whitening on / off 0: Whitening off 1: Whitening on 5:4 PKT_FORMAT[1:0] 3 0 (00) R/W Format of RX and TX data Setting Packet format 0 (00) Normal mode, use FIFOs for RX and TX 1 (01) Synchronous serial mode, Data in on GDO0 and data out on either of the GDOx pins 2 (10) Random TX mode; sends random data using PN9 generator. Used for test.
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CC1101 0x0B: FSCTRL1 – Frequency Synthesizer Control Bit Field Name Reset R/W Description R0 Not used 0 R/W Reserved 15 (0x0F) R/W The desired IF frequency to employ in RX. Subtracted from FS base frequency in RX and controls the digital complex mixer in the demodulator. 7:6 5 4:0 FREQ_IF[4:0] f IF  f XOSC  FREQ _ IF 210 The default value gives an IF frequency of 381kHz, assuming a 26.0 MHz crystal.
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CC1101 0x10: MDMCFG4 – Modem Configuration Bit Field Name Reset R/W 7:6 CHANBW_E[1:0] 2 (0x02) R/W 5:4 CHANBW_M[1:0] 0 (0x00) R/W Description Sets the decimation ratio for the delta-sigma ADC input stream and thus the channel bandwidth. BWchannel  f XOSC 8  (4  CHANBW _ M )·2CHANBW _ E The default values give 203 kHz channel filter bandwidth, assuming a 26.0 MHz crystal.
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CC1101 0x12: MDMCFG2 – Modem Configuration Bit Field Name Reset R/W Description 7 DEM_DCFILT_OFF 0 R/W Disable digital DC blocking filter before demodulator. 0 = Enable (better sensitivity) 1 = Disable (current optimized). Only for data rates ≤ 250 kBaud The recommended IF frequency changes when the DC blocking is disabled. Please use SmartRF Studio [5] to calculate correct register setting.
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CC1101 0x13: MDMCFG1– Modem Configuration Bit Field Name Reset R/W Description 7 FEC_EN 0 R/W Enable Forward Error Correction (FEC) with interleaving for packet payload 0 = Disable 1 = Enable (Only supported for fixed packet length mode, i.e. PKTCTRL0.
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CC1101 0x15: DEVIATN – Modem Deviation Setting Bit Field Name Reset 7 6:4 DEVIATION_E[2:0] 4 (100) 3 2:0 DEVIATION_M[2:0] 7 (111) R/W Description R0 Not used. R/W Deviation exponent. R0 Not used. R/W TX 2-FSK/ GFSK/ 4-FSK Specifies the nominal frequency deviation from the carrier for a ‘0’ (-DEVIATN) and ‘1’ (+DEVIATN) in a mantissa-exponent format, interpreted as a 4-bit value with MSB implicit 1.
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CC1101 0x16: MCSM2 – Main Radio Control State Machine Configuration Bit Field Name Reset 7:5 R/W Description R0 Not used 4 RX_TIME_RSSI 0 R/W Direct RX termination based on RSSI measurement (carrier sense). For ASK/OOK modulation, RX times out if there is no carrier sense in the first 8 symbol periods. 3 RX_TIME_QUAL 0 R/W When the RX_TIME timer expires, the chip checks if sync word is found when RX_TIME_QUAL=0, or either sync word is found or PQI is set when RX_TIME_QUAL=1.
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CC1101 0x17: MCSM1– Main Radio Control State Machine Configuration Bit Field Name Reset 7:6 5:4 3:2 CCA_MODE[1:0] RXOFF_MODE[1:0] 3 (11) 0 (00) R/W Description R0 Not used R/W Selects CCA_MODE; Reflected in CCA signal R/W Setting Clear channel indication 0 (00) Always 1 (01) If RSSI below threshold 2 (10) Unless currently receiving a packet 3 (11) If RSSI below threshold unless currently receiving a packet Select what should happen when a packet has been received Setting Next stat
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CC1101 0x18: MCSM0– Main Radio Control State Machine Configuration Bit Field Name Reset 7:6 5:4 FS_AUTOCAL[1:0] 0 (00) R/W Description R0 Not used R/W Automatically calibrate when going to RX or TX, or back to IDLE Setting When to perform automatic calibration 0 (00) Never (manually calibrate using SCAL strobe) 1 (01) When going from IDLE to RX or TX (or FSTXON) 2 (10) When going from RX or TX back to IDLE automatically 3 (11) Every 4th time when going from RX or TX to IDLE automatically
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CC1101 0x19: FOCCFG – Frequency Offset Compensation Configuration Bit Field Name Reset 7:6 R/W Description R0 Not used 5 FOC_BS_CS_GATE 1 R/W If set, the demodulator freezes the frequency offset compensation and clock recovery feedback loops until the CS signal goes high. 4:3 FOC_PRE_K[1:0] 2 (10) R/W The frequency compensation loop gain to be used before a sync word is detected. 2 1:0 FOC_POST_K FOC_LIMIT[1:0] 1 2 (10) R/W R/W Setting Freq.
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CC1101 0x1A: BSCFG – Bit Synchronization Configuration Bit Field Name Reset R/W Description 7:6 BS_PRE_KI[1:0] 1 (01) R/W The clock recovery feedback loop integral gain to be used before a sync word is detected (used to correct offsets in data rate): 5:4 3 2 1:0 BS_PRE_KP[1:0] BS_POST_KI BS_POST_KP BS_LIMIT[1:0] 2 (10) 1 1 0 (00) R/W R/W R/W R/W Setting Clock recovery loop integral gain before sync word 0 (00) KI 1 (01) 2KI 2 (10) 3KI 3 (11) 4KI The clock recovery feedbac
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CC1101 0x1B: AGCCTRL2 – AGC Control Bit Field Name Reset R/W Description 7:6 MAX_DVGA_GAIN[1:0] 0 (00) R/W Reduces the maximum allowable DVGA gain.
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CC1101 0x1C: AGCCTRL1 – AGC Control Bit Field Name Reset 7 R/W Description R0 Not used 6 AGC_LNA_PRIORITY 1 R/W Selects between two different strategies for LNA and LNA 2 gain adjustment. When 1, the LNA gain is decreased first. When 0, the LNA 2 gain is decreased to minimum before decreasing LNA gain.
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CC1101 0x1D: AGCCTRL0 – AGC Control Bit Field Name Reset R/W Description 7:6 HYST_LEVEL[1:0] 2 (10) R/W Sets the level of hysteresis on the magnitude deviation (internal AGC signal that determine gain changes).
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CC1101 0x1F: WOREVT0 –Low Byte Event0 Timeout Bit Field Name Reset R/W Description 7:0 EVENT0[7:0] 107 (0x6B) R/W Low byte of EVENT0 timeout register. The default EVENT0 value gives 1.0s timeout, assuming a 26.0 MHz crystal. 0x20: WORCTRL – Wake On Radio Control Bit Field Name Reset R/W Description 7 RC_PD 1 R/W Power down signal to RC oscillator. When written to 0, automatic initial calibration will be performed 6:4 EVENT1[2:0] 7 (111) R/W Timeout setting from register block.
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CC1101 0x21: FREND1 – Front End RX Configuration Bit Field Name Reset R/W Description 7:6 LNA_CURRENT[1:0] 1 (01) R/W Adjusts front-end LNA PTAT current output 5:4 LNA2MIX_CURRENT[1:0] 1 (01) R/W Adjusts front-end PTAT outputs 3:2 LODIV_BUF_CURRENT_RX[1:0] 1 (01) R/W Adjusts current in RX LO buffer (LO input to mixer) 1:0 MIX_CURRENT[1:0] 2 (10) R/W Adjusts current in mixer 0x22: FREND0 – Front End TX Configuration Bit Field Name Reset LODIV_BUF_CURRENT_TX[1:0] 1 (0x01) 7:6 5:4
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CC1101 0x24: FSCAL2 – Frequency Synthesizer Calibration Bit Field Name Reset 7:6 R/W Description R0 Not used 5 VCO_CORE_H_EN 0 R/W Choose high (1) / low (0) VCO 4:0 FSCAL2[4:0] 10 (0x0A) R/W Frequency synthesizer calibration result register. VCO current calibration result and override value. Fast frequency hopping without calibration for each hop can be done by calibrating upfront for each frequency and saving the resulting FSCAL3, FSCAL2 and FSCAL1 register values.
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CC1101 29.2 Configuration Register Details – Registers that Loose Programming in SLEEP State 0x29: FSTEST – Frequency Synthesizer Calibration Control Bit Field Name Reset R/W Description 7:0 FSTEST[7:0] 89 (0x59) R/W For test only. Do not write to this register. 0x2A: PTEST – Production Test Bit Field Name Reset R/W Description 7:0 PTEST[7:0] 127 (0x7F) R/W Writing 0xBF to this register makes the on-chip temperature sensor available in the IDLE state.
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CC1101 0x2E: TEST0 – Various Test Settings Bit Field Name Reset R/W Description 7:2 TEST0[7:2] 2 (0x02) R/W The value to use in this register is given by the SmartRF Studio software [5]. 1 VCO_SEL_CAL_EN 1 R/W Enable VCO selection calibration stage when 1 0 TEST0[0] 1 R/W The value to use in this register is given by the SmartRF Studio software [5]. 29.
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CC1101 0x35 (0xF5): MARCSTATE – Main Radio Control State Machine State Bit Field Name Reset 7:5 4:0 MARC_STATE[4:0] R/W Description R0 Not used R Main Radio Control FSM State Value State name State (Figure 25, page 50) 0 (0x00) SLEEP SLEEP 1 (0x01) IDLE IDLE 2 (0x02) XOFF XOFF 3 (0x03) VCOON_MC MANCAL 4 (0x04) REGON_MC MANCAL 5 (0x05) MANCAL MANCAL 6 (0x06) VCOON FS_WAKEUP 7 (0x07) REGON FS_WAKEUP 8 (0x08) STARTCAL CALIBRATE 9 (0x09) BWBOOST SETTLING 10 (0x0A) FS_
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CC1101 0x38 (0xF8): PKTSTATUS – Current GDOx Status and Packet Status Bit Field Name 7 Reset R/W Description CRC_OK R The last CRC comparison matched. Cleared when entering/restarting RX mode. 6 CS R Carrier sense. Cleared when entering IDLE mode. 5 PQT_REACHED R Preamble Quality reached. If leaving RX state when this bit is set it will remain asserted until the chip re-enters RX state (MARCSTATE=0x0D). The bit will also be cleared if PQI goes below the programmed PQT value.
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CC1101 0x3D (0xFD): RCCTRL0_STATUS – Last RC Oscillator Calibration Result Bit Field Name Reset 7 6:0 RCCTRL0_STATUS[6:0] R/W Description R0 Not used R Contains the value from the last run of the RC oscillator calibration routine. For usage description refer to Application Note AN047 [4]. 30 Soldering Information The recommendations for lead-free reflow in IPC/JEDEC J-STD-020 should be followed.
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CC1101 32 References [1] CC1101EM 315 - 433 MHz Reference Design (swrr046.zip) [2] CC1101EM 868 – 915 MHz Reference Design (swrr045.zip) [3] CC1101 Errata Notes (swrz020.pdf) [4] AN047 CC1100/CC2500 – Wake-On-Radio (swra126.pdf) [5] SmartRF [6] CC1100 CC2500 Examples Libraries (swrc021.zip) [7] CC1100/CC1150DK, CC1101DK, and CC2500/CC2550DK Examples and Libraries User Manual (swru109.pdf) [8] DN010 Close-in Reception with CC1101 (swra147.
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CC1101 33 General Information 33.1 Document History Revision Date Description/Changes SWRS061I 2013.11.05 Updated the package designator from RTK to RGP Changed description of VERSION. Reset value changed from 0x04 to 0x14 SWRS061H 2012.10.09 Added 256 Hz clock to Table 41: GDOx Signal Selection SWRS061G 2011.07.26 SWRS061F 2010.01.
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CC1101 Revision Date Description/Changes SWRS061D 2008.05.22 Edited title and removed CC logo. Formatted and edited text. Put important notes in boxes. Corrected the 250 kBaud settings information from MSK to GFSK. Added plot over RX current variation versus input power level and temperature. Added tables for sensitivity, output power and TX current consumption variation versus temperature and supply voltage. Moved the selectivity plots to the electrical specification section and updated the 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 9-May-2015 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
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