User's Manual

Digital UHF Transmitter Chapter 4, Circuit Descriptions
DT835A, Rev. 1 4-5
will occur, thus lowering the
temperature of the assembly.
The +12 VDC enters the board at J2
and is filtered by L1 and C1 before it is
applied to the remaining circuits on the
board.
4.3.4 (A13) PLL Board (1286-1104;
Appendix D)
The PLL board is part of the phase lock
loop (PLL) circuit, which provides the
automatic frequency control (AFC)
voltage, that connects to the VCXO
assembly, and maintains the accurate
output frequency of the VCXO. The AFC
is generated by comparing a sample of
the 10-MHz reference to a sample of
the VCXO frequency. The PLL board
uses an external 10-MHz signal as the
reference unless it is missing, then an
internally generated 10-MHz signal is
used. The two 10-MHz reference
signals are connected to the K1 relay
and the selected reference to U1. The
switching between the two references
is accomplished by the K1 relay which,
when energized, applies the external
10-MHz reference to U1, as long as an
externally generated 10-MHz reference
signal is present and an interlock is
connected to J8, pin 1.
If the interlock is removed or the
external 10-MHz reference is missing,
the relay is de-energized and the
internal 10-MHz reference is applied
through the relay to U1. The internally
generated 10-MHz reference connects
from J7 to pins 3 and 6 of relay K1. The
externally generated 10-MHz reference
connects from J2 to pins 2 and 5 of
relay K1. The unused 10-MHz reference
is connected through the relay to R10,
a 51-Ω load.
With the relay energized, the internally
generated 10-MHz reference from J7
connects through the closed contact of
the relay from pin 6 to pin 7 to R10,
the 51-Ω load. The externally
generated 10-MHz from jack J2
connects through the closed contact of
the relay from pin 2 to pin 1 to
amplifier U1. With the relay not
energized, the internally generated 10-
MHz reference from J7 connects
through the closed contact of the relay
from pin 3 to pin 1 to amplifier U1. The
externally generated 10-MHz from jack
J2 connects through the closed contact
of the relay from pin 5 to pin 7 to R10,
the 51-Ω load.
External 10-MHz Reference Present
Circuitry
The external 10-MHz reference signal
enters the board at J2 and is filtered by
C4, L2, and C5 before it is connected to
the K1 relay. A sample of the 10 MHz is
rectified by CR3 and connected to U3A.
If the sample level of the external 10
MHz is above the reference set by R13
and R14, which is connected to pin 2 of
U3A, the output of U3A stays high. The
high connects to gates of Q4 and Q9,
which are biased on and cause their
drains to go low. The low from the
drain of Q9 is wired to J8, pin 6, for
connection to a remote external 10-
MHz present indicator. The low from
the drain of Q4 connects to the green
LED DS2 which lights to indicate that
an external 10-MHz reference is
present. The low from the drain of Q4
also connects to the gate of Q5, biasing
it off and causing its drain to go high.
This high reverse biases CR4 and allows
a high to be applied to the gates of Q6,
Q8, and Q3, if an interlock, low, is
present at J8, pin 1. The high to the
gate of Q6 biases it on and causing its
drain to go low; the low is connected to
the green LED DS3, which lights,
indicating that an external 10-MHz
reference is selected. The high to the
gate of Q8 biases it on and applies a
low to J8, pin 7, for connection to a
remote reference select indicator. The
high that is applied to the gate of Q3
biases it on and causes its drain to go
low, which energizes the K1 relay and