User's Manual

Digital UHF Transmitter Chapter 4, Circuit Descriptions
DT835A, Rev. 1 4-3
the FPGA. The output of the pulse
shaping filters is then applied to a Pre-
Distortion Linearizer chip, U4, which
can be used to correct for
nonlinearities in the data transmission
path. The output of the Pre-Distortion
chip is gain scaled and output to a dual
D/A converter that output a baseband
I and Q analog signal.
4.2.1.3 Analog Output Section
The baseband I and Q signals from the
D/A converter are applied to
differential analog filters that remove
some of digital artifacts from the D/A
conversion process. The output of the
I channel filter is then mixed with the
pilot frequency, 46.69 MHz, using
mixer U30. The output of the Q filter
is mixed with the pilot frequency that
is phase shifted 90 degrees using
mixer U34. The mixers are current
driven devices so that when the
outputs of U30 and U34 are connected
together, they provide a combined
output. This combined output is
subsequently input to a final
differential output filter which provides
the final IF output at the SMA
connector, J38. This output is
connected through a RG-174 cable to
the BNC connector J4, the IF output
jack, located on the rear panel of the
tray.
4.2.1.4 Pilot Frequency Generation
The 46.69 MHz pilot signal, which is
used in the mixing process, is
generated from a 46.69 MHz VCXO
that is phase locked to a 10 MHz
reference. The VCXO and the 10 MHz
are divided down to a common
frequency, which is then compared
internal to the FPGA. The FPGA
subsequently provides error signals to
a analog phase locked implemented
with op amp stages U45-A, B and C.
The output of these compensation
stages is used as the control voltage to
the VCXO, U37. The phase locked
output of U37 is applied to a analog
filter to remove harmonics of the pilot
and then input to quadrature splitter
Z1. The outputs of Z1 are used as the
inputs to the mixers in the analog
output section.
4.2.2 (A2) DM8-R Front Panel
Board (1307113; Appendix D)
The front panel board contains four
LEDs, Power, MPEG, PLL A and PLL B,
which are viewable on the front panel.
J2 connects to the Modulator Board,
which controls the operation of the
LEDs. When the system is operation
normally, all LEDs will be Green. If a
problem occurs, that LED will not be
lit.
4.3 (A4) UHF Exciter Tray (1142445
or 1294-1111; Appendix C)
4.3.1 (A12 and A18) UHF Filter
(1007-1101; Appendix D)
The UHF filter is a tunable two-section
cavity filter that is typically tuned for a
bandwidth of 5 MHz and has a loss of -
1 dB through the filter.
4.3.2 (A15-A1) UHF Generator
Board (1565-1109; Appendix D)
The UHF generator board is mounted in
the UHF Generator Enclosure (1519-
1144) for EMI and RFI protection. The
board contains a VCXO circuit and
additional circuitry to multiply the VCXO
frequency by eight. The VCXO produces
an output of ≈ 67 MHz to 132 MHz,
depending on the desired channel
frequency. Course adjustment to the
frequency is made by C11, while fine
adjustments are accomplished by the
AFC voltage from (A11) the PLL board
(1286-1104). The VCXO frequency level
is adjusted by C6, L2, and L4. The
output is split and provides an input to
the x8 multiplier circuitry as well as a
sample for the PLL board.