User Manual

DM8-R Digital Modulator Tray Board Descriptions
DM8-R Digital Modulator, Rev. 0 3
DM8-R Modulator Board Configuration
The Digital Modulator Board in the DM8-R is setup through a configuration header
located on the board. The configuration header contains 8 jumper positions between
pins on J26 and J27. The functions of these positions are given in Table 1.
Table 1 J26/J27 Configuration Header Definition
Function when
Jumper Position
Jumper Is Present Jumper Not Present
1 Header Enabled RS485 Enabled
2 CW Zero Normal Mode
3 Internal PRBS External Source
4 Linear Equalizer On Linear Equalizer Off
5 Nonlinear Off Nonlinear On
6 Preset Table 1 Preset Table 2
7 AGC Tracking AGC Fixed
8 Spare
Detailed Circuit Descriptions
Digital Modulator Board (1304884)
SMPTE-310 Input
The DM8-R modulator accepts a SMPTE-310 input the BNC Jack J2 located on the rear
panel of the tray. This input is connected to J42 on the Digital Modulator Board via a
RG-179 cable. This input is applied to a high speed window comparator that adjusts the
level to a low voltage TTL signal to be used by the Altera FPGA, U3. The SMPTE-310
signal is input to the FPGA to recover the clock and the data. A portion of the clock and
recovery circuit is performed by a high speed comparator, U17, that functions as an
external delay circuit.
Channel Coder
The FPGA subsequently uses the SMPTE-310 clock and data as the input to the channel
coder contained inside the FPGA. The channel coder is a series of DSP blocks defined by
the ATSC standard for 8 VSB data transmission. These blocks include the data
randomizer, Reed Solomon Encoder, data interleaver, trellis coder, and sync insertion.
The channel coder portion inside the FPGA generates the 8 distinct levels in an 8 VSB
transmitter. These levels are subsequently input to a linear equalizer that provides for
frequency response correction in the transmission path. The linear equalizer is a 67 tap
FIR filter that is loaded with tap values from the microntroller, U1, located on this board.
The output of the linear equalizer is then input to two pulse shaping filters, an in phase
(I) and a quadrature (Q) filter that are also located inside the FPGA. The pulse shaping
filters are FIR filters that have fixed tap values that are preset inside the FPGA. The
output of the pulse shaping filters is then applied to a Pre-Distortion Linearizer chip, U4,
which can be used to correct for nonlinearities in the data transmission path. The
output of the Pre-Distortion chip is gain scaled and output to a dual D/A converter that
output a baseband I and Q analog signal.