User's Manual

300-Watt Digital UHF Transmitter Chapter 4, Circuit Descriptions
DT830A, Rev. 1 4-30
A sample of the reflected power output of
the tray is applied to jack J2-1 and J2-2
of the board from the dual peak detector
board, single supply. The reflected power
sample is connected through R21 and
R22 to U1B, a buffer amplifier. The
output of U1B is split, with one part going
to the VSWR threshold circuit, another
sample connected to J2-5 for remote
metering, and the final sample applied to
the meter at position 2 on S2, the front
panel meter switch. R22 can be adjusted
to calibrate the % Reflected Power
indication on the front panel meter.
A sample of the AGC voltage level at R20
on the board is connected through a
divider network consisting of R87, R88,
R19, and R18 to the meter at position 1
of S2, the front panel meter switch.
4.3.11.5 Operational Voltages
The voltage input to the board is +26
VDC from the switching power supply.
The +26 VDC connects to the board at
J6-1 and is wired to U4, which is a 3-
terminal regulator IC that takes the +26
VDC input and produces the +12 VDC
needed for the operation of the board.
The +12 VDC from U4 is connected
through CR6 to U5, which is a +5-VDC
regulator that takes the +12 VDC input
from U4, or the transmitter control board
in the UHF exciter tray, through J6, pin 3,
and produces a +5-VDC output that is
applied to the rest of the board. This +12
VDC is connected to U5, a regulator IC,
which produces a +5-VDC output that is
applied to the Enable and
Overtemperature LEDs that operate even
when the +26-VDC input to the board
from the switching power supply is
removed.
4.3.12 (A4-A1) Single Stage
Amplifier Assembly, Class A;
Appendix D)
The single stage UHF amplifier assembly,
class A is made from the generic single
stage amplifier board, class A (1265-
1415). The assembly uses a single
PTB20101 Ericsson device, made up of
two transistors in parallel, and operating
class A to amplify the signal by
approximately +11 dB. Bias adjust pot
R6 sets the operating current for Q1.
4.3.12.1 Q1 and Associated Circuitry
The RF input signal connects to SMA jack
J1 on the board. The RF input is applied
through an AC coupling and DC blocking
capacitor (C1 to L1) and associated
circuitry to form a balun. The balun
converts the input signal from a 50-Ω
unbalanced impedance to a 12.5-Ω
balanced impedance configuration with
the two outputs, applied to the bases of
Q1, 180° out of phase with each other.
C3, C4, C6, and C5, which can be
adjusted for peak output, are for
impedance matching to the input of the
parallel transistors that make up Q1. The
base circuit is RF bypassed by C2, C7,
C17, and C29.
The collectors are impedance matched to
12.5Ω by C22, C23, and C19, which can
be adjusted for peak output with the best
linearity. C25 provides AC coupling and
DC blocking for the output signal to SMA
RF output connector J2. L2 and
associated circuitry form a balun that
transforms the two balanced signals back
to a single, unbalanced 50-Ω impedance
output. The collector circuit is RF
bypassed by C9, C12 to C15, C18, C21,
C24, C26, C30, and C31.
The +26 VDC needed for biasing Q1 is
applied to E1, which is the high side of
A4-A4. E1 is a .5-Ω/2-watt external
metering resistor that is mounted on the
heatsink next to the single stage
amplifier assembly. The metering resistor
is in the collector circuit of the RF
transistor, Q1, and provides the main
current path for Q1. The base bias
applied to Q1 is supplied through R11,
R4, R2, and R3.
The collector bias voltage drop across the
A4-A4 metering resistor is in parallel with