User's Manual

300-Watt Digital UHF Transmitter Chapter 4, Circuit Descriptions
DT830A, Rev. 1 4-22
indicator is driven from U4, pin 60,
through field effect transistors (FETs) Q2
to J9-4. The 10-MHz reference present
indicator is driven from the collector of
Q1 through transistor Q3 and associated
components to J9-2.
The +12 and -12 VDC source is supplied
at J2. The +5 VDC is supplied at J1. L2,
L3, C13, C21, and C23 are for filtering.
4.2.4 (A3) LED Board (1561-1204;
Appendix D)
The LED board provides front-panel
verification of the status of the MPEG
input signal, 10-MHz reference signal,
phase-locked status of the IF oscillator,
and the +5-VDC power supply.
DS1 is driven from the VSB modulator
board (1561-1201) that provides a
constant +5 VDC to J1-1 and a logic low
at J1-2 when the MPEG input signal is
present. DS2 is driven from the local
oscillator board (1561-1203) that
provides a constant +5 VDC and a logic
low at J1-4 when the 10-MHz reference
signal is present at the oscillator board.
DS3 is driven from the local oscillator
board that provides a constant +5 VDC
and a logic low at J1-6 when the IF
oscillator is phase locked. DS4 is driven
from the +5 VDC source on the DC
power supply board (1520-1103)
through J1-7.
4.2.5 (A11) VSB Modulator Interface
Board (1561-1205; Appendix D)
The VSB modulator interface board
interfaces with the external MPEG source
to the VSB modulator board (1561-
1201) in the front of the tray. The
interface board receives MPEG either at
J11 in the Society for Motion Picture and
Television Engineers (SMPTE) format, at
J1 in differential emitter-to-coupler logic
(ECL) format, or at J2 in differential
transistor-to-transistor logic (TTL)
format and converts it to single-ended
TTL. The output is in the form of data
(J10) and a clock (J3). The jumpers at
J13 and J14 on this card select between
the various input formats. These jumper
settings are outlined in Chapter 5,
Detailed Alignment Procedures, of this
manual. Jumpers J4 through J7 were
used during the initial design of the
board and have been preset at the
factory. These four jumpers should all
be placed in positions 1-2 with the
exception of jumper J6, which should be
placed in position 2-3. Jumper block J15
was also used in the initial design of the
board and should be set to position 3.
This card also provides the capability for
a future parallel interface. This future
parallel interface can be in either a TTL
or ECL format. Test connector J8 will be
used for the future parallel interfaces.
Note: This future interface will
utilize the PLL Locked LED at the
bottom, right-hand corner of this
board; the LED will not illuminate
with the existing interfaces.
The board is supplied by a –12-VDC and
a +5-VDC source. Regulator U16
converts the -12 VDC to a -5.2-VDC
source.
4.2.6 (A5) VSB Filter Board (1561-
1301; Appendix D)
The VSB filter board performs the digital
pulse-shaping filter function of the ATSC
specification. The board receives
equalized symbol data at J1 and applies
it to an I pulse-shaping filter and a Q
pulse-shaping filter. The I filter is
implemented in U1 and U2 and the Q
filter is implemented in U3 and U4. The
pulse-shaping filter outputs are applied
to D/A converters through jumper blocks
J25 and J28. The output of the D/A
converters is filtered to remove the
32.28-MHz converter update rate. The I
data is available at J26 and the Q data is
available at J29.