User's Manual

300-Watt Digital UHF Transmitter Chapter 4, Circuit Descriptions
DT830A, Rev. 1 4-11
motor-driven pot controlled by switch S1
on the board or screwdriver adjust pot
R1 on the front panel of the UHF exciter
tray. An external power raise/lower
switch can be used by connecting it to
jack J10, at J10-11 power raise, J10-13
power raise/lower return, and J10-12
power lower on the rear of the UHF
exciter tray.
S1, or the remote switch, controls relays
K1 and K2 which, in turn, the control
motor M1 that moves variable resistor
R75. If the (optional) remote power
raise/lower kit is not purchased, the ALC
voltage is controlled only by screwdriver
adjust pot R1 on the front panel of the
UHF exciter tray. The ALC voltage is set
for .8 VDC at TP4 with 0 dBm output at
J12 of the board. A sample of the ALC at
J19, pin 2, is wired to the transmitter
control board where it is passed on to the
front panel meter and the AGC circuits.
The ALC voltage and the DC level
corresponding to the IF level after signal
correction are fed to U10A, pin 2, whose
output at pin 1 connects to the ALC pin-
diode attenuator circuit. If there is a loss
of gain somewhere in an IF circuit, the
output power of the transmitter will drop,
which the ALC circuit senses at U10A,
automatically lowering the loss of the
pin-diode attenuator circuit and
increasing the gain to compensate.
The ALC action starts with the ALC
detector level that is monitored at TP4.
The detector output at TP4 is nominally
+.8 VDC and is applied through resistor
R77 to a summing point at op-amp
U10A, pin 2. The current available from
the ALC detector is offset, or
complimented, by current that is taken
away from the summing junction. In
normal operation, U10A, pin 2, is at 0
VDC when the loop is satisfied. If the
recovered or peak-detected IF signal at
IF input jack J7 of this board should drop
in level, which would normally mean that
the output power is decreasing, the null
condition would no longer occur at U10A,
pin 2. When the level drops, the output
of U10A at pin 1 will go more positive
and, if jumper W3 on J6 is in the
Automatic position, it will cause ALC pin-
diode attenuators CR1, CR2, and CR3 to
have less attenuation. This will increase
the IF level and compensate for the
decrease in level. If the ALC cannot
sufficiently increase the input level to
satisfy the ALC loop, because of not
enough range, an ALC fault will occur.
The fault is generated because U10D, pin
12, increases above the trip point set by
R84 and R83 until it conducts. This
makes U10D, pin 14, high, and lights the
red ALC Fault LED DS2 on the board.
4.1.7.10 For Scrambled Operation with
Encoding
For encoded, or scrambled, operation,
jumper W4 on J8 must be connected
between pins 2 and 3; jumper W8 on J9
must be between pins 3 and 2; jumper
W7 on J26 must be between pins 2 and
3; and jumper W5 on J21 must be
between pins 2 and 3. The IF is
connected through W4 on J8 to the sync-
regeneration circuits.
If this board is operated with scrambling,
using suppressed sync, the ALC circuit
operates differently than just described,
because there is no peak-of-sync present
on the IF input. A timing pulse from the
scrambling encoder connects to the
board at J24. This timing pulse is
converted to sync pulses by U17A and
U17B, controlling the operation of Q8.
The sync amplitude is controlled by
R149, which is then applied to U15A
where it is added to the detected IF
signal to produce a peak-of-sync level.
The output of U15A is peak detected by
CR26 and fed to U15B. If necessary,
intercarrier notch L39 can be placed in
the circuit by placing W6 on J22. The
intercarrier notch is adjusted to filter any
aural and 4.5-MHz intercarrier
frequencies. The peak-of-sync signal is
fed through R162, the ALC calibration
control, to amplifier U15C. The amplified
peak-of-sync output is connected
through J21, pins 2 and 3, to U10A,
where it is used as the reference for the