User's Manual

300-Watt Digital UHF Transmitter Chapter 4, Circuit Descriptions
DT830A, Rev. 1 4-2
exactly on frequency. Capacitors C4 and
C5 provide the positive feedback
necessary for oscillation.
The output of the oscillator is buffered by
Q2 and Q3. L4 and C12 form a 40-MHz
bandpass filter. The 40-MHz signal
passes through a digital divider IC U4,
which divides the signal down to 10 MHz.
Transistor Q5 provides a buffered, 10-
MHz output at jack J1.
The crystal is heated in an enclosed
crystal oven (HR-1) that is internally set
at 60° C. The oscillator board is heated
by a separate oven that is set at 50° C.
U1 is a temperature sensor/controller IC
that monitors the temperature of the
oscillator assembly and controls the
operation of Q4 and U2. The operating
temperature of the assembly is set by
adjusting R15. If the temperature of the
assembly falls below 50° C, U1 will bias
Q4 on, which in turn increases the
amount of current flow through U2.
The flange of U2 is thermally connected
to the heatsink of the assembly. The
temperature of the heatsink will increase
as the current through U2 increases. As a
result, U2 will dissipate more power in
the form of heat, and the temperature of
the assembly will increase. If the
assembly temperature rises above 50° C,
the opposite action will occur, thus
lowering the temperature of the
assembly.
The +12 VDC enters the board at J2 and
is filtered by L1 and C1 before it is
applied to the remaining circuits on the
board.
4.1.4 (A13) PLL Board (1286-1104;
Appendix D)
The PLL board is part of the phase lock
loop (PLL) circuit, which provides the
automatic frequency control (AFC)
voltage, that connects to the VCXO
assembly, and maintains the accurate
output frequency of the VCXO. The AFC
is generated by comparing a sample of
the 10-MHz reference to a sample of the
VCXO frequency. The PLL board uses an
external 10-MHz signal as the reference
unless it is missing, then an internally
generated 10-MHz signal is used. The
two 10-MHz reference signals are
connected to the K1 relay and the
selected reference to U1. The switching
between the two references is
accomplished by the K1 relay which,
when energized, applies the external 10-
MHz reference to U1, as long as an
externally generated 10-MHz reference
signal is present and an interlock is
connected to J8, pin 1.
If the interlock is removed or the
external 10-MHz reference is missing, the
relay is de-energized and the internal 10-
MHz reference is applied through the
relay to U1. The internally generated 10-
MHz reference connects from J7 to pins 3
and 6 of relay K1. The externally
generated 10-MHz reference connects
from J2 to pins 2 and 5 of relay K1. The
unused 10-MHz reference is connected
through the relay to R10, a 51-Ω load.
With the relay energized, the internally
generated 10-MHz reference from J7
connects through the closed contact of
the relay from pin 6 to pin 7 to R10, the
51-Ω load. The externally generated 10-
MHz from jack J2 connects through the
closed contact of the relay from pin 2 to
pin 1 to amplifier U1. With the relay not
energized, the internally generated 10-
MHz reference from J7 connects through
the closed contact of the relay from pin 3
to pin 1 to amplifier U1. The externally
generated 10-MHz from jack J2 connects
through the closed contact of the relay
from pin 5 to pin 7 to R10, the 51-Ω
load.
External 10-MHz Reference Present
Circuitry
The external 10-MHz reference signal
enters the board at J2 and is filtered by
C4, L2, and C5 before it is connected to
the K1 relay. A sample of the 10 MHz is
rectified by CR3 and connected to U3A. If
the sample level of the external 10 MHz