User's Manual

Innovator CU250ATD, 250 Watt Transmitter Tray Description
Instruction Manual, Rev. 0 11
The channel coder portion, inside the FPGA, generates the 8 distinct levels in an 8
VSB transmitter. These levels are subsequently input to a linear equalizer that
provides for frequency response correction in the transmission path. The linear
equalizer is a 67-tap FIR filter that is loaded with tap values from the
microcontroller, U1, located on this board. The output of the linear equalizer is then
input to two pulse shaping filters, an in phase (I) and a quadrature (Q) filter that are
also located inside the FPGA. The pulse shaping filters are FIR filters that have fixed
tap values that are preset inside the FPGA. The output of the pulse shaping filters is
then applied to a Pre-Distortion Linearizer chip, U4, which can be used to correct for
nonlinearities in the data transmission path. The output of the Pre-Distortion chip is
gain scaled and output to a dual D/A converter, which output a baseband I and Q
analog signal.
The baseband I and Q signals from the D/A converter are applied to differential
analog filters that remove some of digital artifacts from the D/A conversion process.
The output of the I channel filter is then mixed with the pilot frequency, 46.69 MHz,
using mixer U30. The output of the Q filter is mixed with the pilot frequency that is
phase shifted 90 degrees using mixer U34. The mixers are current driven devices so
that when the outputs of U30 and U34 are connected together, they provide a
combined output. This combined output is subsequently input to a final differential
output filter which provides the final IF output at the SMA connector, J38. To
maintain signal integrity, this IF output is connected to the SMA connector J39 with a
small semi-rigid cable assembly. The final IF output then appears at J1-2B.
The 46.69 MHz pilot, that is used in the mixing process is generated from a 46.69
MHz VCXO, U37, that is phase locked to a 10 MHz reference. The VCXO and the 10
MHz are divided down to a common frequency, which is then compared internal to
the FPGA. The FPGA subsequently provides error signals to an analog phase locked
implemented with op amp stages U45-A, B and C. The output of these compensation
stages is used as the control voltage to the VCXO, U37. The phase locked output of
U37 is applied to an analog filter to remove harmonics of the pilot and then input to
the quadrature splitter Z1. The outputs of Z1 are used as the inputs to the mixers in
the analog output section.
(A3) IF Pre-Corrector Board (1308796)
This IF output (0 dBm) of the 8 VSB Modulator connects to J2 on the (A3) IF Pre-
Corrector Board (1308796), which provides response, in phase and quadrature pre-
correction to the IF signal. The Pre-Corrected IF output at J1 is cabled to the IF In
Jack on (A4) the Digital Agile Upconverter Board, which up converts the IF to the On
Channel RF signal that is cabled to the RF Out Jack of the board. The RF out is
connected to J1 the RF input jack on the ALC board. The (A5) ALC Board,
(1308570), is used to control the RF drive power to the RF amplifier chain in the
transmitter. The board accepts an 8-VSB RF input signal at J1, the RF input jack, at
a nominal input level of -3 dBm average power and amplifies it to whatever drive
level is necessary to drive the final RF amplifier in the tray to full power. The RF
output of the ALC board at J2, typically 0 to +10 dBm, is cabled to J1 on the
Amplifier Assembly.
(A6) Amplifier Assembly (1308867)
The (A6) Amplifier Assembly (1308867) is made up of (A6-A1) the 2 Stage UHF
Amplifier Board, (1308784) and (A6-A2) the RF Module Pallet w/Philips transistors
(1300116). The assembly has approximately 36 dB of gain.