User's Manual

Innovator CU250ATD, 250 Watt Transmitter Tray Description
Instruction Manual, Rev. 0 10
CU250ATD Innovator 250-Watt Transmitter
Figure 1: Front View of 30W Driver Tray.
30W Driver Tray Description
The Driver Tray accepts an RF On Channel signal (-79 to –8 dBm) and converts it to
a DTV RF On Channel output signal at 30 Watts. The transmitter provides linear and
nonlinear correction capability for the transmission path as well as internal test
sources that are used during initial transmitter installation.
(A1) 8 VSB Demodulator Board (1308275)
The RF input to the Transmitter is connected to the J1 BNC connector located on the
rear panel of the tray. This RF signal is wired to (A1) the 8 VSB demodulator board
(1308275), which generates a SMPTE-310 output at J13. The (A1) 8 VSB
demodulator assembly receives an off air 8 VSB signal on any VHF or UHF channel
and demodulates this to an MPEG-2 transport stream that is per the SMPTE-310M
standard. The input to the assembly is at an “F” style connector on the shielded
tuner and can be at a level of –78 dBm to –8 dBm. The tuner (TU1) down converts
the RF channel to a 44 MHz IF signal. This IF signal is the input to the digital
receiver chip U1. The digital receiver chip subsequently decodes the IF and delivers
an MPEG-2 transport stream, on a parallel data bus, to a programmable logic array,
U8. U8 clocks the asynchronous MPEG data from the receiver chip and outputs a
synchronous data stream at a 19.39 MHz rate to buffer/driver U11. U11
subsequently drives the output at J13 to a lower level that is AC coupled out of the
board and is cabled to J42 on the 8 VSB Modulator Board.
(A2) 8 VSB Modulator Board (1304883)
The (A2) 8 VSB Modulator Board (1304883) accepts the SMPTE-310 MPEG data
stream input at the SMA connector J42 and produces a 6 MHz wide IF output, at the
IF Output Jack J38. The IF output is centered at 44 MHz using a pilot carrier of
46.69 MHz generated on the board.
This SMPTE-310 MPEG data stream input is applied to a high-speed window
comparator U21 that adjusts the level to a low voltage TTL signal to be used by the
Altera FPGA, U3. The SMPTE-310 signal is input to the FPGA to recover the clock
and the data. A portion of the clock and recovery circuit is performed by a high-
speed comparator, U17, which functions as an external delay circuit.
The FPGA subsequently uses the SMPTE-310 clock and data as the input to the
channel coder contained inside the FPGA. The channel coder is a series of DSP
blocks defined by the ATSC standard for 8 VSB data transmission. These blocks
include the data randomizer, Reed Solomon Encoder, data interleaver, trellis coder,
and sync inserter.