User's Manual

Innovator CU5-1800BTD/BRD ATSC Transmitter/ Board Descriptions
Regenerative Translator
Instruction Manual, Rev. 0 43
Channel Coder
The FPGA subsequently uses the SMPTE-310 clock and data as the input to the channel
coder contained inside the FPGA. The channel coder is a series of DSP blocks defined by
the ATSC standard for 8 VSB data transmission. These blocks include the data
randomizer, Reed Solomon Encoder, data interleaver, trellis coder, and sync inserter.
The channel coder portion inside the FPGA generates the 8 distinct levels in an 8 VSB
system. These levels are subsequently input to a linear equalizer that provides for
frequency response correction in the transmission path. The linear equalizer is a 67 tap
FIR filter that is loaded with tap values from the microcontroller, U1, located on this
board. The output of the linear equalizer is then input to two pulse shaping filters, an in
phase (I) and a quadrature (Q) filter that are also located inside the FPGA. The pulse
shaping filters are FIR filters that have fixed tap values that are preset inside the FPGA.
The output of the pulse shaping filters is then applied to a Pre-Distortion Linearizer chip,
U4, which can be used to correct for nonlinearities in the data transmission path. The
output of the Pre-Distortion chip is gain scaled and output to a dual D/A converter,
which output a baseband I and Q analog signal.
Analog Output Section
The baseband I and Q signals from the D/A converter are applied to differential analog
filters that remove some of digital artifacts from the D/A conversion process. The output
of the I channel filter is then mixed with the pilot frequency, 46.69 MHz, using mixer
U30. The output of the Q filter is mixed with the pilot frequency that is phase shifted 90
degrees using mixer U34. The mixers are current driven devices so that when the
outputs of U30 and U34 are connected together, they provide a combined output. This
combined output is subsequently input to a final differential output filter which provides
the final IF output at the SMA connector, J38. To maintain signal integrity, this IF
output is connected to the SMA connector J39 with a small semi-rigid cable assembly.
The final IF output then appears at J1-2B.
Pilot Frequency Generation
The 46.69 MHz pilot, which is used in the mixing process, is generated from a 46.69
MHz VCXO, U37 that is phase locked to a 10 MHz reference. The VCXO and the 10 MHz
are divided down to a common frequency, which is then compared internal to the FPGA.
The FPGA subsequently provides error signals to an analog phase locked implemented
with op amp stages U45-A, B and C. The output of these compensation stages is used
as the control voltage to the VCXO, U37. The phase locked output of U37 is applied to
an analog filter to remove harmonics of the pilot and then input to the quadrature
splitter Z1. The outputs of Z1 are used as the inputs to the mixers in the analog output
section.
Voltage Requirements
The ±12 VDC and +5VDC needed for operation of the board connect to J1 on the Power
Conditioner Board which delays the +5VDC so that the ±12 VDC to the 8 VSB Modulator
Board is applied first. The voltage output of the power conditioner board is at J2 that is
jumpered to J30 on the 8 VSB modulator board.
The ±12 VDC connect to the 8 VSB modulator board at J30-1. The +12V SYS connects to
J18A, B & C and to regulator circuits. The +12V SYS is filtered by L2, L3, C105 and C106