User's Manual

Innovator CU0TD-1/CU0RD-1 – CU4TD/CU4RD Board Descriptions
ATSC Transmitter/Regenerative Translator
Instruction Manual, Rev. 1 56
(A2) Digital Modulator (1316332)
SMPTE-310 or ASI input
The digital modulator board accepts a SMPTE-310 or ASI input at the SMA
connector J42 from the 8 VSB demodulator board in a RD system or directly from
the RF input jack on the rear panel of the drawer in a TD system. This input is
applied to a high speed window comparator U21 that adjusts the level to a low
voltage TTL signal to be used by the Altera FPGA, U3. The SMPTE-310 signal is
input to the FPGA to recover the clock and the data. A portion of the clock and
recovery circuit is performed by a high-speed comparator, U17, which functions
as an external delay circuit.
Channel Coder
The FPGA subsequently uses the SMPTE-310 clock and data as the input to the
channel coder contained inside the FPGA. The channel coder is a series of DSP
blocks defined by the ATSC standard for 8 VSB data transmission. These blocks
include the data randomizer, Reed Solomon Encoder, data interleaver, trellis
coder, and sync inserter.
The channel coder portion inside the FPGA generates the 8 distinct levels in an 8
VSB system. These levels are subsequently input to a linear equalizer that
provides for frequency response correction in the transmission path. The linear
equalizer is a 67 tap FIR filter that is loaded with tap values from the
microcontroller, U1, located on this board. The output of the linear equalizer is
then input to two pulse shaping filters, an in phase (I) and a quadrature (Q) filter
that are also located inside the FPGA. The pulse shaping filters are FIR filters
that have fixed tap values that are preset inside the FPGA. The output of the
pulse shaping filters is then applied to a Pre-Distortion Linearizer chip, U4, which
can be used to correct for nonlinearities in the data transmission path. The
output of the Pre-Distortion chip is gain scaled and output to a dual D/A
converter, which output a baseband I and Q analog signal.
Analog Output Section
The baseband I and Q signals from the D/A converter are applied to differential
analog filters that remove some of digital artifacts from the D/A conversion
process. The output of the I channel filter is then mixed with the pilot frequency,
46.69 MHz, using mixer U30. The output of the Q filter is mixed with the pilot
frequency that is phase shifted 90 degrees using mixer U34. The mixers are
current driven devices, therefore when the outputs of U30 and U34 are connected
together, they provide a combined output. This combined output is subsequently
input to a final differential output filter which provides the final RF output at the
SMA connector, J38. To maintain signal integrity, this RF output is connected to
the SMA connector J39 with a small semi-rigid cable assembly. The final RF
output then appears at J1-2B.
Pilot Frequency Generation
The on channel pilot, which is used in the mixing process, is generated from a
VCXO, U37 that is phase locked to a 10 MHz reference. The VCXO and the 10