User's Manual

Innovator CHV400BTD ATSC Transmitter Board Descriptions
Technical Manual, Rev. 0 54
The output of U3B connects through S1 pins 2 to 3, if it is in the ALC position, to the pin-
diode attenuator circuit, CR1, CR2 & CR3. The high forward biases them more or less,
that increases or decreases the IF level, therefore the output level. When the input signal
level increases, the forward bias on the pin attenuator decreases, therefore the output
power decreases, that maintains the output power as set by the customer.
The ALC voltage is set for 1.0 VDC at TP1 with a –12 dBm peak sync output as measured
at J1 of the board. The ALC action starts with the ALC detector level monitored at TP1.
The detector output at TP1 is nominally, 1.0 VDC, and is applied through resistor R33 to a
summing point at op-amp U3B pin 6. The current available from the ALC detector is
offset, or complemented, by current taken away from the summing junction. In normal
operation, U3B pin 6, is at 0 VDC when the loop is satisfied. If the recovered or peak-
detected IF signal level at the IF input to this board should drop, which normally indicates
that the output power has decreased, the null condition no longer occurs at U3B pin 6.
When the level drops, the output of U3B pin 7 goes more positive. If S1 is in the
Automatic position, it will cause the ALC pin-diode attenuators CR1, CR2, and CR3 to have
less attenuation and therefore increase the IF level that will compensate for the decrease
in the output power level.
If the ALC cannot increase the input level enough to satisfy the ALC loop, due to the lack
of range, an ALC fault will occur. The fault is generated because U3C pin 9, increases
above the trip point set by R47 and R50 until it conducts. This makes U3C pin 8, high and
causes Q3 to conduct, which lights the Red ALC Fault LED DS1.
Input Fault and Modulation Fault Circuitry
The input IF signal at Z1 Port 1 connects to the input and modulation fault circuitry at
T2. T2 doubles the voltage swing by means of a 1:4 impedance transformation. The
output is connected to a detector circuit, consisting of R54, CR6, R58 and C19. The
detected IF level output is amplified by U4A and then split. There is a Test Point at TP3
for a voltage reference check of the input level.
One output of U4A is connected to the detector CR5 that produces a Peak Sync Voltage,
which is applied to the Op-Amp U12A. The detector provides a reference that
determines the IF signal level at the input to the Board. The operation of the Threshold
Detector is as follows. The Minimum IF Input level at TP3 is fed through detector CR5 to
the Op-Amp IC U12A Pin 2. The reference voltage for the Op-Amp is determined by the
voltage divider consisting of R52 and R57 off the +12 VDC line. When the detected
input signal level at U12A Pin 2 falls below this reference threshold, approximately 10 dB
below the normal input level, the output of U12A at Pin 1, goes to the +12 VDC Rail.
This High is connected to the Gate of Q4 which forward biases it and creates a current
path from the +12 VDC line through the Red LED DS2, the Input Level Fault Indicator
which lights, and the Transistor Q4 to Ground. The High also connects through the
diode CR7 to the Gate of Q6 that conducts and connects a low to J7-1, Input Loss, which
is wired to the Control Board for control and monitoring.
The Video Input Level at TP3 is also fed to a modulation loss circuit consisting of the IC
U4B, U12B and associated component. When the input signal level to the U4B falls
below the reference set by R62 and R60, which acts as a loss of Modulation Detector,
the output of U4B, goes high which is split. One part biases On the Transistor Q9. A
current path is then established from the +12 VDC line, the resistors R63 and R64, the
Red LED DS3, the Modulation Loss Indicator, which lights, through Q9 to ground. The