Assembly Instructions Chapter 4

4-6 kW UHF Translator Chapter 4, Circuit Descriptions
837B, Rev. 0 4-9
board. If the 4.5-MHz composite input
kit is purchased, the 4.5-MHz
composite signal at J22 connects to the
external composite 4.5-MHz filter board
and the 4.5-MHz bandpass filter board.
These two boards provide the video-
only signal to J27 and the 4.5-MHz
intercarrier signal to J28 from the 4.5-
MHz composite input. The video
through video gain pot R12 (adjusted
for 1 Vpk-pk at TP2) connects to
amplifier U1B.
The output of U1B, if the delay
equalizer board is present in the tray,
connects the video from J6, pin 2, to
the external delay equalizer board and
back to the sync tip clamp/modulator
board at J6, pin 4. If the delay
equalizer board is not present, the
video connects through jumper W1 on
J5, pins 1 and 2. The delay equalizer
board plugs directly to J6 on the sync
tip clamp/modulator board. The video
from J6, pin 4, is then connected
through jumper W1 on J5, pins 2 and
3, to amplifier Q1. The output of Q1
connects to Q2; the base voltage of Q2
is set by the DC offset voltage output of
the sync tip clamp circuit.
4.2.2.2 Sync Tip Clamp Circuit
The automatic sync tip clamp circuit is
made up of U4A, Q7, U3B, and
associated components. The circuit
begins with a sample of the clamped
video that is split off from the main
video path at the emitter of Q3. The
video sample is buffered by U3A and
connected to U4A. The level at which
the tip of sync is clamped,
approximately -1.04 VDC as measured
at TP2, is set by the voltage-divider
network connected to U4A. If the video
level changes, the sample applied to
U4A changes. If jumper W7 on J4 is in
the Clamp-On position, the voltage
from the clamp circuit that is applied to
the summing circuit at the base of Q2
will change; this will bring the sync tip
level back to approximately -1.04 VDC.
Q7 will be turned off and on according
to the peak of sync voltage level that is
applied to U4A. The capacitors C14,
C51, C77, and C41 will charge or
discharge to the new voltage level,
which biases U3B more or less, through
jumper W7 on J4 in the Auto Clamp-On
position. U3 will increase or decrease
its output, as needed, to bring the peak
of sync back to the correct level as set
by R152 and R12. This voltage level is
applied through U3B to Q2. In the
Manual position, jumper W7 on J4 is in
the Clamp-Off position, between pins 1
and 2, and adjustable resistor R41
provides the manual clamp bias
adjustment for the video that connects
to Q2.
Jumper W6 on jack J35 must be in the
Normal position, between pins 2 and 3,
for the clamp circuit to operate with a
normal non-scrambled signal. If a
scrambled signal is used, the tray is
operated with jumper W6 in the
Encoded position, connected between
pins 1 and 2. The clamp circuit is set by
adjusting depth of modulation pot R152
for the correct depth of modulation as
measured at TP2.
Depending on the input video level, the
waveform as measured at TP2 may not
be 1 Vpk-pk. If W7 on J4 is moved to
the Clamp-Off (Manual) position,
between pins 1 and 2, the clamp level
is adjusted by R41 and will not
automatically be clamped to the set
level. The output of buffer amplifier
U3A drives the sync tip clamp circuit
that consists of differential amplifier
U4A, field effect transistor (FET) Q7,
and buffer amplifier U3B. U4A is biased
by R124, R125, R184, R152, and R126
so that the clamped voltage level at
peak of sync is approximately -1.04
VDC as measured at TP2.
4.2.2.3 Main Video Signal Path (Part 2
of 2)
The clamped video from Q2 is
connected to white clipper circuit Q3.
Q3 is adjusted with R20 and set to