Assembly Instructions Chapter 4

4-6 kW UHF Translator Chapter 4, Circuit Descriptions
837B, Rev. 0 4-8
compared in the IC and the fV, and fR
is applied to the differential amplifier
U3B. The output of U3B is fed back
through CR17 to the 4.5-MHz VCO IC
U10; this sets up a PLL circuit. The 4.5-
MHz VCO will maintain the extremely
accurate 4.5-MHz separation between
the visual and aural IF signals; any
change in frequency will be corrected
by the AFC error voltage.
PLL chip U5 also contains an internal
lock detector that indicates the status
of the PLL circuit. When U5 is in a
"locked" state, pin 28 goes high and
causes the green LED DS1 to
illuminate. If the 4.5-MHz VCO and the
45.75-MHz oscillator become
"unlocked," out of the capture range of
the PLL circuit, pin 28 of U5 will go to a
logic low and cause the red LED DS2 to
light. A mute output signal from Q3
(unlock mute) will be applied to jack
J9. This mute is connected to the
transmitter control board.
4.2.1.6 Voltage Requirements
The ±12 VDC needed for the operation
of the board enters through jack J1.
The +12 VDC is connected to J1-3 and
filtered by L2, C3, and C4 before it is
connected to the rest of the board. The
-12 VDC is connected to J1-5 and
filtered by L1, C1, and C2 before it is
connected to the rest of the board. The
+12 VDC is connected to U8 and U9;
these are 5-volt regulator ICs that
provide the voltage to the U10 and U5
ICs.
4.2.2 (A5) (Optional) Sync Tip
Clamp/ Modulator Board (1265-
1302; Appendix D)
The sync tip clamp/modulator board is
made up of five circuits: the main video
circuit, the sync tip clamp circuit, the
visual modulator circuit, the aural IF
mixer circuit, and the diplexer circuit.
The sync tip clamp/modulator board
takes the baseband video or 4.5-MHz
composite input that is connected to
the video input jack (either J1 or J2,
which are loop-through connected) and
produces a modulated visual IF + aural
IF output at output jack J20 on the
board. The clamp portion of the board
maintains a constant peak of sync level
over varying average picture levels
(APL). The modulator portion of the
board contains the circuitry that
generates an amplitude-modulated
vestigial sideband visual IF signal
output that is made up of the baseband
video input signal (1 Vpk-pk)
modulated onto an externally
generated 45.75-MHz IF carrier
frequency. The visual IF signal and the
aural IF signal are then combined in the
diplexer circuit to produce the visual IF
+ aural IF output that is connected to
J20, the IF output jack of the board.
4.2.2.1 Main Video Signal Path (Part 1
of 2)
The baseband video or the 4.5-MHz
composite input connects to the board
at J2. J2 is loop-through connected to
J1 and terminated to 75 watts if jumper
W4 is on jack J3. With jumper W4
removed, the input can be connected to
another translator through J1; J1 is
loop-through connected to J2.
Test point TP1 is provided to monitor
the level of the input. The input is fed
to the non-inverting and inverting
inputs of U1A, a differential amplifier
that minimizes any common-mode hum
that may be present on the incoming
signal. Diodes CR1 to CR4 form a
voltage-limiter network in which, if the
input voltages exceed the supply
voltages for U1A, the diodes conduct,
preventing damage to U1A. CR1 and
CR3 conduct if the input voltage
exceeds the negative supply and CR2
and CR4 conduct if the input voltage
exceeds the positive supply voltage.
The video output of U1A is connected
to J22 on the board. Normally, the
video at J22 is jumpered to J27 on the